SNLS666 January   2020 SN75LVPE4410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7.5.1.2 SMBUS/I2C Register Control Interface

If EN_SMB = L3 (SMBus / I2C control mode), the SN75LVPE4410 is configured through a standard I2C or SMBus interface that may operate up to 400 kHz. The slave address of the SN75LVPE4410 is determined by the pin strap settings on the EQ1_ADDR1 and EQ0_ADDR0 pins. The device can be configured for best signal integrity and power settings in the system using the I2C or SMBus interface. The sixteen possible slave addresses (8-bit) for the SN75LVPE4410 are shown in Table 5.

Table 5. SMBUS/I2C Slave Address Settings

EQ1_ADDR1 PIN LEVEL EQ0_ADDR0 PIN LEVEL 8-BIT WRITE ADDRESS (HEX) 7-BIT ADDRESS (HEX)
L0 L0 0x30 0x18
L0 L1 0x32 0x19
L0 L2 0x34 0x1A
L0 L3 0x36 0x1B
L1 L0 0x38 0x1C
L1 L1 0x3A 0x1D
L1 L2 0x3C 0x1E
L1 L3 0x3E 0x1F
L2 L0 0x40 0x20
L2 L1 0x42 0x21
L2 L2 0x44 0x22
L2 L3 0x46 0x23
L3 L0 0x48 0x24
L3 L1 0x4A 0x25
L3 L2 0x4C 0x26
L3 L3 0x4E 0x27
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