ZHCSN45B December 2021 – December 2023 SN75LVPE5412
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
In PCIe Gen 3.0, 4.0, and 5.0 applications, the specification requires RX-TX link training to establish and optimize signal conditioning settings at 8.0, 16.0, and 32.0Gbps, respectively. In link training, the RX partner requests a series of FIR – pre-shoot and de-emphasis coefficients (10 presets) from the TX partner. The RX partner includes CTLE and DFE. The link training would pre-condition the signal, with an equalized link between the Root Complex and Endpoint.
Note: there is no link training in PCIe Gen 1.0 (2.5Gbps) or PCIe Gen 2.0 (5.0Gbps) applications. The SN75LVPE5412 is placed in between the TX and RX. It helps extend the PCB trace reach distance by boosting the attenuated signals with its equalization, which allows the user to recover the signal by the downstream RX more easily.
For operation in Gen 5.0, 4.0, and 3.0 links, the SN75LVPE5412 transmit outputs are designed to pass the TX Preset signaling onto the RX for the PCIe Gen 5.0, 4.0, and 3.0 link to train and optimize the equalization settings. The suggested setting for the device is GAIN = L4 (default). Adjustments to the EQ setting should be performed based on the channel loss to optimize the eye opening in the RX partner. The TX equalization presets or CTLE and DFE coefficients in the RX can also be adjusted to further improve the eye opening.