If MODE = L2 (SMBus / I²C secondary control mode), the SN75LVPE5421 is configured for best signal integrity through a standard I²C or SMBus interface that may operate up to 400 kHz. The secondary address of the SN75LVPE5421 is determined by the pin strap settings on the ADDR and MODE pins. Table 6-5 provides the eight possible secondary addresses (7-bit) for each channel banks of the device. In SMBus/I²C modes the SCL, SDA pins must be pulled up to a 3.3V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7kΩ is a good first approximation for a bus capacitance of 10pF.

The SN75LVPE5421 has two types of registers:

• Shared Registers: These registers can be accessed at any time and are used for device-level configuration, status read back, control, or to read back the device ID information.
• Channel Registers: These registers are used to control and configure specific features for each individual channel. All channels have the same register set and can be configured independent of each other or configured as a group through broadcast writes to Bank 0 or Bank 1.

The SN75LVPE5421 features two banks of channels, Bank 0 (Channels 0-1) and Bank 1 (Channels 2-), each featuring a separate register set and requiring a unique SMBus secondary address.