ZHCSN44B December   2021  – December 2023 SN75LVPE5421

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Five-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
      4. 6.3.4 Receiver Detect State Machine
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Active Buffer Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe x8 Lane Switching
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Protocol Agnostic Linear Redriver for High Speed Interfaces
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RUA|42
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5.2.1 Shared Registers

Table 6-6 General Registers (Offset = 0xE2)
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 rst_i2c_regs R/W/SC 0x0 Device reset control: Reset all I2C registers to default values (self-clearing).
5 rst_i2c_mas R/W/SC 0x0 Reset I2C Primary (self-clearing).
4-0 RESERVED R 0x0000 Reserved
Table 6-7 DEVICE_ID0 Register (Offset = 0xF0)
Bit Field Type Reset Description
7-4 RESERVED R 0x0001 Reserved
3 device_id0_3 R 0x1 Device ID0 [3:1]: 101
2 device_id0_2 R 0x0 see MSB
1 device_id0_1 R 0x1 see MSB
0 RESERVED R X Reserved
Table 6-8 DEVICE_ID1 Register (Offset = 0xF1)
Bit Field Type Reset Description
7 device_id[7] R 0x0 Device ID 0010 1000: SN75LVPE5421
6 device_id[6] R 0x0 see MSB
5 device_id[5] R 0x1 see MSB
4 device_id[4] R 0x0 see MSB
3 device_id[3] R 0x1 see MSB
2 device_id[2] R 0x0 see MSB
1 device_id[1] R 0x0 see MSB
0 device_id[0] R 0x1 see MSB
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