ZHCSKM5 December 2019 TAS2110
PRODUCTION DATA.
The TAS2110 can operate using one of four selectable device addresses. In TDM/I2S Mode, audio input and output are provided via the FSYNC, SBCLK, SDIN and SDOUT pins using formats including I2S, Left Justified and TDM. Configuration and status are provided via the SDA and SCL pins using the I2C protocol. Table 1 below illustrates how to select the device I2C address. I2C slave addresses are shown as 7-bit address format.
I2C SLAVE ADDRESS | AD1 PIN | AD0 PIN |
---|---|---|
0x48 (global address)
|
NA | NA |
0x4C
|
GND | GND |
0x4D
|
GND | VDD |
0x4E
|
VDD | GND |
0x4F
|
VDD | VDD |
The TAS2110 has a global 7-bit I2C address 0x48. When enabled the device will additionally respond to I2C commands at this address regardless of the AD1 and AD0 pin settings. This is used to speed up device configuration when using multiple TAS2110 devices and programming similar settings across all devices. The I2C ACK / NACK cannot be used during the multi-device writes since multiple devices are responding to the I2C command. The I2C CRC function should be used to ensure each device properly received the I2C commands. At the completion of writing multiple devices using the global address, the CRC at I2C_CKSUM register should be checked on each device using the local address for a proper value. The global I2C address can be disabled using I2C_GBL_EN register. The I2C address is detected by sampling the address pins when SDZ pin is released. Additionally, the address may be re-detected by setting I2C_AD_DET high after power up and the pins will be resampled.
I2C_GBL_EN | SETTING |
---|---|
0
|
Disabled |
1
|
Enabled (default) |
I2C_AD_DET | SETTING |
---|---|
0
|
normal (default) |
1
|
Re-detect |