ZHCSKM5 December 2019 TAS2110
PRODUCTION DATA.
The power rail may be brought up and down in any order. There is no requirement on sequencing. However if VDD is present without VBAT an additional rise in VDD current will be observed until VBAT is present.
When the supplies have settled, the SDZ terminal can be set HIGH to operate the device. Additionally the SDZ pin can be tied to VDD and the internal POR will perform a reset of the device. After a hardware or software reset additional commands to the device should be delayed for 100 uS to allow the OTP to load. The above sequence should be completed before any I2C operation.
In External PVDD Case, User need to ensure that PVDD does not drop below VBAT-0.7V.