8.4.4 Boost
The TAS2110 internal processing algorithm automatically enables the boost when needed. A look-ahead algorithm monitors the battery voltage and the digital audio stream. When the speaker output approaches the battery voltage the boost is enabled in-time to supply the required speaker output voltage. When the boost is no longer required it is disabled and bypassed to maximize efficiency. The boost can be configured in one of two modes. The first is low in-rush (Class-G) supporting only boost on-off and has the lowest in-rush current. The second is high-efficiency (Class-H) where the boost voltage level is adjusted to a value just above what is needed. This mode is more efficient but has a higher in-rush current to quickly transition the levels. This can be configured using Table 78.
Table 78. Boost Mode
BST_MODE[1:0] |
BOOST MODE |
00
|
Class-H - High efficiency (default) |
01
|
Class-G - Low in-rush |
10
|
Always On |
11
|
Always Off - Pass-through |
The boost can be enabled and disabled using BST_EN register. When driving the Class-D amplifier using an external supply through the PVDD pin, the boost should be disabled and the VBST pin can be left floating. Do not drive an external voltage on the VBST pin. When suppling and external PVDD voltage the VBAT voltage must also be supplied to the device. While VBAT supply must be present it will not carry current to the speaker load.
Table 79. Boost Enable
BST_EN |
BOOST IS |
0
|
Disabled |
1
|
Enabled (default) |
Table 80. Active Mode PFM Lower Frequency Limit
BST_PFML[1:0] |
LOWER LIMIT (Hz) |
00
|
No lower limit |
01
|
25 kHz |
10
|
50 kHz (default) |
11
|
100 kHz |
The boost has a soft-start to limit in-rush current during the initial charge. The current limit and soft-start timer are configurable to adjust to system component selection.
Table 81. Soft-Start Current Limit
BST_SSL[1:0] |
CURRENT LIMIT (A) |
00
|
Disabled - Boost Normal Limit |
01
|
1.0 A |
10
|
1.5 A (default) |
11
|
2 A |
Table 82. Class-G Soft-Start Timer
BST_GSST[1:0] |
TIMEOUT (s) |
00
|
1 * BST_HSTT |
01
|
2 * BST_HSTT |
10
|
4 * BST_HSTT(default) |
11
|
8 * BST_HSTT |
Table 83. Class-H Soft-Start Timer
BST_HSST[3:0] |
TIMEOUT (s) |
0x0
|
9 µS |
0x1
|
18 µS |
0x2
|
36 µS |
0x3
|
54 µS |
0x4
|
72 µS |
0x5
|
90 µS |
0x6
|
108 µS |
0x7
|
135 µS (default) |
0x8
|
162 µS |
0x9
|
198 µS |
0xA
|
252 µS |
0xB
|
342 µS |
0xC
|
477 µS |
0xD
|
612 µS |
0xE
|
792 µS |
0xF
|
990 µS |
The boost inductor and decoupling capacitor range needs to be specified using BST_IR and BST_LR registers. These setting optimize the boost to ensure current limit accuracy and avoid clipping in class-H operation.
Table 84. Boost Inductor Range
BST_IR[1:0] |
INDUCTANCE (H) |
00
|
< 0.6 µH |
01
|
0.6 µH-1.3 µH (default) |
10
|
1.3 µH - 2.5 µH |
11
|
Reserved |
Table 85. Boost Load Regulation
BST_LR |
VALUE |
00
|
Reserved |
01
|
3A/V; load regulation = 1V (default) |
10
|
2A/V; load regulation = 1.5V |
11
|
Reserved |
The maximum boost voltage regulation is set by BST_VREG. When operating in class-G mode the boost when needed will be at this voltage. In class-H mode of operation the boost voltage is automatically selected based on the audio signal but, will not exceed this set value.
The peak current limits the boost current drawn from the VBAT supply. This setting allows flexibility in the inductor selection for various saturation currents. The current limit can be adjust in 45 mA steps with register BST_ILIM[5:0]. The peak current limit setting is the maximum and may be temporarily reduced if the and ICLA current limit is active.
Table 86. Peak Current Limit
BST_ILIM[5:0] |
CURRENT (A) |
0x00-0x08
|
Reserved |
0x09
|
1.48 A |
0x0A
|
1.54 A |
...
|
... |
0x36
|
3.96 A (default) |
0x37
|
4 A |
0x38-0x3F
|
Reserved |
For multiple parts the TAS2110 can shift the boost phase to ensure each device will contribute to the load sharing. The boost syncing among multiple devices is enabled using BST_SYNC and then each part is configured to be on 0 or 180 phase using BST_PA. This avoids peak current align on and clock edges and spreads out battery ripple. The phase of additional devices can be set relative to the master using register BST_PA[1:0]. The phase align is performed over the Inter-chip Communication (ICC) bus and a slot for this feature needs to be configured if enabled.
Table 87. Boost Sync
BST_SYNC |
|
0
|
Not Synced (default) |
1
|
Synced to FSYNC |
Table 88. Boost Phase
BST_PA[0] |
PHASE (Deg) |
0
|
~0° (default) |
1
|
~180° |