SLASFC6 August 2024 TAS2120
ADVANCE INFORMATION
TAS2120 supports flexible operating mode transition from active to shutdown and vice-verse using ASI clock auto detection feature. When MODE[1:0] is configured as '11' the device toggles between Active and Software shutdown state based on valid ASI clock signals applied on the ASI input pins, ie BCLK and FSYNC. If no ASI clocks are detected in this mode, the device remains in software shutdown, with software shutdown mode IQ on VDD pin, until a valid BCLK and FSYNC clock is detected. Once a valid clock is detected, the device is powered up in active state until the clocks are valid or device is shutdown using software or hardware shutdown commands.
The device can detect and raise interrupt flags on detection of incorrect clock configurations based on status of CLK_ERR_PWR_EN. When this bit is set high, the device monitors for activity on the clock pins and flags any error using the latched interrupts status register. The device can also raise interrupts using IRQZ pin based on status of the corresponding interrupt MASK registers. When the error protection bit is enabled, if a clock error is detected, the device will automatically shutdown with proper shutdown sequencing and minimize any clicks and pops due to invalid clocks.
When the device is in shutdown state, the clock error detection can be delayed to provide system with time required to settle the input clocks. This power up delay in clock error detection is controlled using an internal pre-power up clock error detection timer configured by CLK_HALT_TIMER. If device doesn't detect a valid clock at the end of the CLK_HALT_TIMER expiry, the Pre-Power-up Clock error is flagged on INT_LTCH4[2] bit, and corresponding interrupt can be generated on IRQZ pin based on status of INT_MASK4[2] bit. When MODE[1:0] is configured as '11' (Wake-up on ASI mode), CLK_HALT_TIMER of '000' is not recommended and it stops the device from entering the software shutdown and increases the VDD IQ while the device is shutdown.
Once the device is powered up, the external and internally generated clocks are constantly monitored based on status of CLK_ERR_PWR_EN bit. If enabled, any error in external or internal clock is flagged using the clock error status register INT_LTCH2[3] bit, and corresponding interrupt can be generated on IRQZ pin based on status of INT_MASK2[3].
For system flexibility, the device will also set the error status for the type of detected clock error. The device can also be configured to raise an interrupt on IRQZ pin for any specific type of clock error, instead of using the generic clock error interrupt generation. Table 6-44 below explains the different type of clock errors and corresponding status bits and interrupt MASK register bits. One or more register bits in the table below can be set based on the type of clock error detected.
If the device shuts down due to any type of clock error, it can attempt to re-power itself automatically when MODE[1:0] is set to '11'.
| CLK_ERR_PWR_EN | Setting |
|---|---|
| 0 | Disabled |
| 1 | Enabled (default) |
| CLK_HALT_TIMER[2:0] | Setting |
|---|---|
| 000 | Disabled (infinite time). |
| 001 | 0.8 ms (default) |
| 010 | 3.2 ms |
| 011 | 34.1 ms |
| 100 | 68.3 ms |
| 101 | 256 ms |
| 110 | 768 ms |
| 111 | 1.3 s |
| Clock error type | Description | Status flag register bit | IRQZ generation Mask bit |
|---|---|---|---|
| Clock error | Clock error for any internal or external clocking configuration errors. This bit will be set along with specific clock errors detected in the rest of the table below except for Pre-Power-up Clock errors. | INT_LTCH2[3] | INT_MASK2[3] |
| Pre-Power-up Clock error | Clock error detected during shutdown mode after clock error is detected at end of CLK_HALT_TIMER. | INT_LTCH4[2] | INT_MASK4[2] |
| Clock ratio change error | Clock error detected due to on the fly change in FSYNC to SBCLK ratio. | INT_LTCH2[2] | INT_MASK2[2] |
| Fs change error | Clock error detected due to on the fly change in FSYNC clock frequency | INT_LTCH2[1] | INT_MASK2[1] |
| Fs invalid error | Clock error detected due to incorrect FSYNC clock frequency | INT_LTCH2[0] | INT_MASK2[0] |
| Frame out of sync | Clock error detected due to Frame out of sync | INT_LTCH2[5] | INT_MASK2[5] |
| Internal PLL Clock error | Clock error detected due to internally generated clock frequency error. | INT_LTCH2[4] | INT_MASK2[4] |
The device also has a digital watchdog timer which monitors for errors in the internal digital state machine and shuts down the device on detection of such errors. This error can also raise an interrupt on IRQZ pin and flag to the host device of the error state.