SLASFC6 August   2024 TAS2120

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
          3. 6.3.1.4.3 VDD Y-bridge
          4. 6.3.1.4.4 Class-H Boost
        5. 6.3.1.5 2S Battery Mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Boost
      5. 6.4.5 Supply Voltage Monitors
      6. 6.4.6 Thermal Protection
      7. 6.4.7 Clocks and PLL
        1. 6.4.7.1 Auto clock based wakeup and clock errors
      8. 6.4.8 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Mono/Stereo Configuration
        2. 7.2.2.2 Boost Converter Passive Devices
        3. 7.2.2.3 EMI Passive Devices
        4. 7.2.2.4 Miscellaneous Passive Devices
      3. 7.2.3 Application Performance Plots
  9. Power Supply Recommendations
  10. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

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订购信息

2S Battery Mode

TAS2120 can be configured to function for different battery systems like single series cell (1S) Li-ion battery (2.5 V to 5.5 V) or 2-series cell (2S) series cell battery (4.7 V to 10 V). When the 2S battery is selected for the device, the diagram below shows the conceptual connections in the system to connect the 2S battery. When selected for 2S battery operation, the VBAT pin of the device is used for biasing internal blocks and needs to be supplied from external power source between 3.0 V to 5.5 V.

The internal battery voltage monitor needs to be switched to sense the voltage on the VBAT_SNS pin instead of the default sensing done on the VBAT pin. SEL_VBAT_MODE[1:0] configures the internal voltage monitor and the device configuration between 1S or 2S battery systems.

When SEL_VBAT_MODE[1:0] is set as '10', ie 2S mode of operation, the device internal bias voltage needs to be configured based on VBAT_BIAS_SELx registers. If the VBAT pin voltage is available from the center tap or half of the 2S battery voltage, the VBAT_BIAS_SEL1 needs to be set high. For other VBAT voltage configurations the VBAT_BIAS_SEL1 should be set low and appropriate VBAT_BIAS_SEL2 configuration should be selected.

Table 6-12 Battery mode selection
SEL_VBAT_MODE[1:0] Configuration
00 (default) Voltage monitor on VBAT pin. 1S mode of operation
01 Voltage monitor on VBAT_SNS pin. 1S mode of operation
10 Voltage monitor on VBAT_SNS pin. 2S mode of operation
11 Reserved
Table 6-13 VBAT pin bias voltage selector
VBAT_BIAS_SEL1 Configuration
0 (default) VBAT pin biasing based on VBAT_BIAS_SEL2 register
1 VBAT pin voltage is half of 2S battery voltage
Table 6-14 VBAT pin bias voltage selector
VBAT_BIAS_SEL2[1:0] Configuration
00 Reserved
01(default) Minimum VBAT pin voltage > 2.9V
10 Minimum VBAT pin voltage > 3.3V
11 Minimum VBAT pin voltage > 3.7V