Use wide traces for signals that carry high current and avoid VIAs wherever
possible. If VIAs can't be avoided, multiple VIAs should be added to enable
low parasitic inductance and high current capability. These include traces
for PVDD, VBAT, VDD, PGND, BGND, GND, OUT_P and OUT_N.
PGND and BGND signals should
be directly connected and shorted to the ground plane of board to minimize
parasitic inductance. Common inductance between ground pins (eg GND and PGND
or GND and BGND common routing) before connecting to ground plane should be
avoided.
The coupling between high switching signal traces
like OUT_P, OUT_N, SW should be avoided from sensitive low
voltage signals.
Minimize capacitance between high switching lines
like OUT_P, OUT_N, SW to
ground/static nodes. Larger capacitance will result in efficiency drop. Coupling between
OUT_P and OUT_N will also cause degraded efficiency.
VBAT routing to the boost inductor and the device
VBAT pin should be star connected to the common VBAT
supply plane. Ensure the decoupling capacitor C4 is
placed close to the device and decoupling capacitor
C5 is placed close to the inductor.
Place the boost inductor between VBAT and SW close to the device terminal
with no VIAs between device terminal and the inductor. VBAT routing to the
boost inductor should be routed with minimal routing resistance to achieve
best performance from device.
Decoupling capacitors should be placed close to the device. Smallest
possible package size is recommended for the decaps to achieve best
performance from device. DREG, VDD, IOVDD, VBAT (C4 cap), PVDD low ESL (C6
cap) are recommended to be 0201 case size or lower. VIAs between
decapacitors and device pins should be avoided, or multiple VIAs added to
minimize parasitic inductances.
All decoupling capacitor's
ground terminal should be strongly connected to the ground plane with
multiple ground VIAs. The ground routing loop between the cap ground and the
device ground pins should be minimized.
For VDD Y-bridge functionality, the routing from the host PMIC to the device
VDD should be wide supply plane trace with minimal routing parasitic
inductance.
For the capacitor between
GREG-PVDD (C9 cap), PVDD side of capacitor should not be connected directly
to the PVDD decoupling capacitors (C6, C7 and C8), and should be connected
as close as possible to the device PVDD pin.
In external PVDD mode of operation, SW pin should be left floating and not
connected to any supply or ground signals.