米6体育平台手机版

ZHCSFY2B August 2015 – February 2019 TAS2555

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YZ|42

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7.6 I²C Timing Requirements

For I²C interface signals over recommended operating conditions (unless otherwise noted). Note: All timing specifications are specified by design but not tested at final test. See Figure 1

PARAMETER		TEST CONDITION	Standard-Mode			Fast-Mode			UNITS
PARAMETER		TEST CONDITION	MIN	TYP	MAX	MIN	TYP	MAX	UNITS
f_SCL	SCL clock frequency		0		100	0		400	kHz
t_HD;STA	Hold time (repeated) START condition. After this period, the first clock pulse is generated.		4			0.6			μs
t_LOW	LOW period of the SCL clock		4.7			1.3			μs
t_HIGH	HIGH period of the SCL clock		4			0.6			μs
t_SU;STA	Setup time for a repeated START condition		4.7			0.6			μs
t_HD;DAT	Data hold time: For I²C bus devices		0		3.45	0		0.9	μs
t_SU;DAT	Data set-up time		250			100			ns
t_r	SDA and SCL Rise Time				1000	20 + 0.1 × Cb		300	ns
t_f	SDA and SCL Fall Time				300	20 + 0.1 × Cb		300	ns
t_SU;STO	Set-up time for STOP condition		4			0.6			μs
t_BUF	Bus free time between a STOP and START condition		4.7			1.3			μs
C_b	Capacitive load for each bus line				400			400	pF

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7.6 I2C Timing Requirements

7.6 I²C Timing Requirements