9.4.1.1 Right-Justified Mode (RJF)

Audio Serial Interface 1 can be put into Right Justified Mode by programming B0_P1_R1_D[7:5] = 010 and B0_P1_R2_D[7:5] = 010 . Audio Serial Interface 2 can be put into Right Justified Mode by programmingB0_P1_R21_D[7:5] = 010 and B0_P1_R22_D[7:5] = 010. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

Figure 25. Timing Diagram for Right-Justified Mode

For right-justified mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of the data.