9.4.1.3 I²S Mode

Audio Serial Interface 1 can be put into I²S Mode by programming B0_P1_R1_D[7:5] = 000 and B0_P1_R2_D[7:5] = 000 . Audio Serial Interface 2 can be put into I²S Mode by programming B0_P1_R21_D[7:5] = 000 and B0_P1_R22_D[7:5] = 000. In I²S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.

Figure 29. Timing Diagram for I²S Mode

Figure 30. Timing Diagram for I²S Mode with Offset = 2

Figure 31. Timing Diagram for I²S Mode with Offset = 0 and Inverted Bit Clock

For I²S mode, the number of bit-clocks per channel should be greater than or equal to the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.