9.3.7 PLL

The TAS2560 on-chip PLL generates the necessary internal clock frequency for the audio DAC, I-V sensing ADCs, and DSP. The programmability of the PLL allows TAS2560 operation from a wide variety of clocks that may be available in the system application. The configurable PLL clock path is shown in Figure 30.

Figure 30. PLL_CLK Source and Generation

The PLL input supports clocks varying from 512 kHz to 20 MHz and is register programmable to enable generation of required PLL_CLK from various clocks with fine resolution. The PLL output clock PLL_CLK is determined from PLL_CLKIN using the following formula:

Equation 1.

The PLL multipliers and dividers are program using the register in Table 2. The table includes also the range of values support and the default values. The D-divider value is 14-bits wide and is controlled by 2 registers. For proper update of the D-divider value, PLL_DVAL_1 must be programmed first followed immediately by PLL_DVAL_2. Unless the write to PLL_DVAL_2 is completed, the new value of D will not take effect.

Field PLL_CLK_SRC in register PLL_CLKIN configures the PLL clock input, PLL_CLKIN.

The following conditions must be satisfied in the PLL configuration:

• If D = 0 (Integer Mode), the PLL clock input (PLL_CLKIN) must satisfy:
  
• If D > 0(Fractional Mode), the PLL clock input (PLL_CLKIN) must satisfy:
  
• The PLL output needs to be configured between 100 MHz and 200 MHz

Finally, the PLL_LOWF field in register PLL_JVAL must be configured properly based on the PLL_INPUT_CLK intermediate clock frequency.