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ZHCSF47E June 2016 – December 2017 TAS2560

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9.3.9 Clock Error Detection

TAS2560 has two clock error detection blocks that soft-mute the playback path when errors in the clocking signals occur. Clock error detection 1 block is used for monitoring the audio interfaces. The clock error detection 2 block is used for monitoring the internal clocks for situations where the audio interface clocks are different from the PLL input clock.

Table 6. Clock Error 1 Source

CLK_ERR_1[4] (CLK_E1_SRC)	Input Source
0	ASI_CLK (default)
1	PDM_CLK

Table 7. Clock Error 2 Source

CLK_ERR_1[3:2] (CLK_E2_SRC)	Input Source
00	DAC Modulator Clock (default)
01	ADC Modulator Clock
10	PLL Clock
11	Reserved

The clock error detection blocks may be disabled using field CLK_ERR1_EN and CLK_ERR2_EN. It is recommend to disable these blocks. Both clock error blocks must be enable or disabled together to ensure correct operation. When clock error blocks are enabled the idle channel detection used to reduce power consumption must be disabled. It is recommended to use PurePath Console 3 Software TAS2560 Application software to generate the device configuration files. The following code should be written to disable the idle channel detection block.

#add in dsp memory write section after Device power up and a delay
#assuming B0_P0
w 98 00 32 
w 98 6c 00 00 00 00 # disabling idle channel detect
w 98 00 00

Table 8. Clock Error 1 Enable

CLK_ERR_1[1] (CLK_E1_EN)	Clock Error Detection
0	disabled
1	enabled (default)

Table 9. Clock Error 2 Source

CLK_ERR_1[0] (CLK_E2_EN)	Clock Error Detection
0	disabled
1	enabled (default)

The detection block will trigger when the clock input to the specified detection block is not present within the respective specified time of field CLK_ERR1_TIME or CLK_ERR2_TIME

Table 10. Clock Error 1 Timeout

CLK_ERR_2[5:3] (CLK_E1_TIME)	Timeout
000	11 ms
001	22 ms
010	44 ms
011	87 ms
100	174 ms
101	350 ms
110	700 ms
111	1.2 s (default)

Table 11. Clock Error 2 Timeout

CLK_ERR_2[2:0] (CLK_E2_TIME)	Timeout
000	11 ms
001	22 ms
010	44 ms
011	87 ms
100	174 ms
101	350 ms
110	700 ms
111	1.2 s (default)

When a clocking error is detected the playback will be soft-mute at a rate set by field CLK_ERR_MR in register CLOCK_ERR_CFG_2. The error will be recorded in the sticky register INT_DET_1 and can be reported on the interrupt pin if mask in register INT_CFG_2

Table 12. Clock Error Soft-mute Ramp Rate

CLK_ERR_CFG_2[7:6] (CLK_ERR_MR)	Ramp-down Rate
00	15 us per dB (default)
01	30 us per dB
10	60 us per dB
11	120 us per dB

When the clock is available the system will perform a pop-free un-mute and resume operation.