9.4.1 Audio Digital I/O Interface

Audio data is transferred between the host processor and the TAS2560 via the digital audio serial interface(ASI), or audio bus. The audio bus on this device is flexible, including left or right-justified data options, support for I²S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly. The audio bus of the TAS2560, when using PCM formatted input and/or output, can be configured for left or right-justified, I²S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits where the chip input can be left, right or L+R/2.

In addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse(DSP) or a 50% duty cycle signal(I²S). The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies. Clock sources for Master mode are described in section Clock Distribution. When the audio serial data bus is powered down while configured in master mode, the terminals associated with the interface are put into a Hi-Z output state.

The bit clock is used to clock-in and clock-out the digital audio data across the serial bus. This signal can be programmed to generate variable clock pulses by controlling the bit-clock multiply-divide factor. The number of bit-clock pulses in a frame may need adjustment to accommodate various word-lengths as well as to support the case when multiple TAS2560 devices may share the same audio bus.

The TAS2560 also includes a feature to offset the position of start of data transfer with respect to the word-clock(WCLK). This offset is specified in number of bit-clocks. This can be used in cases where there is a non-zero bit-clock delay from WCLK edge or to support TDM modes of operation. The TAS2560 can place the DOUT line into a Hi-Z (tri-state) condition during all bit clocks when valid data is not being sent. TDM mode is useable with I²S, LJF, RJF, and DSP interface modes and is required for stereo applications when more than one TAS2560 part is used, see Stereo Application Example - TDM Mode. The TAS2560 also has a bus keeper circuit that can be enabled in tri-sate mode. The bus-keeper is a weak internal latch that will hold the data line state without the need for external pull-up or pull-down resistors while signal lines are in the Hi-Z or non-driven state.