9.4.1.1 I²S Mode

In I²S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.

Figure 34. Timing Diagram for I²S Mode

Figure 35. Timing Diagram for I²S Mode with ASI_OFFSET1 = 2

Figure 36. Timing Diagram for I²S Mode with ASI_OFFSET1 = 0 and Inverted Bit Clock

For I²S mode, the number of bit-clocks per channel should be greater than or equal to the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.