The TAS2764 operates using a TDM/I²S interface. Audio input and output are provided via the FSYNC, SBCLK, SDIN and SDOUT pins using formats including I²S, Left Justified and TDM. Configuration and status are provided via the SDA and SCL pins using the I²C protocol.

The table below illustrates how to configure the device for I²C address . The slave addresses are shown left shifted by one bit with the R/W bit set to 0 (i.e. {ADDR[6:0],1b0}). Resistors with tolerance better than 5% must be used for setting the address configuration.

The TAS2764 has a global 7-bit I²C address 0x80. When enabled, the device will additionally respond to I²C commands at this address regardless of the ADDR pin settings. This is used to speed up device configuration when using multiple TAS2764 devices and programming similar settings across all devices. The I²C ACK / NACK cannot be used during the multi-device writes since multiple devices are responding to the I²C command. The I²C CRC function should be used to ensure each device properly received the I²C commands. At the completion of writing multiple devices using the global address, the CRC at I2C_CKSUM register should be checked on each device using the local address for a proper value. The global I²C address can be disabled using I2C_GBL_EN register bit. The I²C address is detected by sampling the ADDR pin when SDZ pin is released. Additionally, the address may be re-detected by setting I2C_AD_DET register bit high after power up and the ADDR pin will be re-sampled.