All supply rails should be bypassed by low-ESR ceramic capacitors as shown in Figure 9-1 and described in Table 9-1.

Place the decoupling capacitors as close as possible to the respective power supply pins. Do not place vias between the decoupling capacitors and the device pin. Connect the vias to the ground or power planes on the far side of the capacitor.

Ground plane in the adjacent layer is recommended. It is required to maintain a single solid ground plane underneath the IC and its decoupling caps. Solid ground plane is the best option, providing continuous (uninterrupted) and low-impedance path for return currents back to the source. Fill the device side layer of the system board with ground copper and connect it to main ground plane using lots of vias. Each ground pin (GND, PGND) should directly shorted to the ground plane in the same layer as device as well as to the main solid ground plane in the adjacent layer through vias.

Specific layout design recommendations should be followed for this device:

• Do not use vias for traces that carry high current: PVDD, VBAT1S, PGND, GND and the speaker OUT_P, OUT_N.
• Connect VSNS_P and VSNS_N as close as possible to the speaker.
• VSNS_P and VSNS_N should be connected between the EMI ferrite filter and the speaker if EMI ferrites are used at the outputs.
• VSNS_P and VSNS_N routing should be separated and shielded from switching signals (interface signals, speaker outputs, bootstrap pins).
• Place bootstrap capacitors as close as possible to the BST pins.