The device enters Hardware Shutdown mode if the SDZ pin is asserted low. In Hardware Shutdown mode, the device consumes the minimum quiescent current from AVDD, VBAT1S and PVDD supplies. All registers loose state in this mode and I²C communication is disabled.

In normal shutdown mode if SDZ is asserted low while audio is playing, the device will ramp down volume on the audio, stop the Class-D switching, power down analog and digital blocks and finally put the device into Hardware Shutdown mode. If configured in normal shutdown mode with timeout the device will force a hard shutdown after a timeout set by the configurable shutdown timer (register bits SDZ_TIMEOUT[1:0]). The device can also be configured for forced hard shutdown and in this case it will not attempt to gracefully disable the audio channel. The shutdown mode can be controlled using SDZ_MODE[1:0] register bits.

When SDZ is released, the device will sample the ADDR pin and enter the software shutdown mode.