The TAS2764 monitors the absolute value of the audio stream.

When the input was initially above the programmed threshold set by LVS_FTH[4:0] register bits the Class D was supplied by PVDD rail. If the signal level drops below this threshold for longer than the hysteresis time defined by LVS_HYS[3:0] bits the Class-D supply will switch to VBAT1S.

The BYP_EN pin will be asserted (open drain released). All values of LVS_HYS[3:0] bit settings will ensure the remaining samples will be output before BYP_EN is asserted. When multiple devices have BYP_EN pin connected together, any device requiring a supply voltage higher than the threshold will pull the open drain output low.

When the signal level crosses above the programmed threshold set by LVS_FTH[4:0] bits the Class-D supply will switch to PVDD.

The open-drain BYP_EN pin will be de-asserted (actively pulling the output low) after a delay programmed by the LVS_DLY[1:0] register bits . The Y Bridge will switch from VBAT1S to PVDD after a delay programmed by the CDS_DLY[1:0] register bits.

LVS threshold is set based on the output signal level and is measured in dBFS.

The LVS threshold can alternately be configured to be a value relative to the VBAT1S voltage. To use the alternate configuration set the LVS_TMODE bit to high and use the LVS_RTH[3:0] register bits for setting the threshold.

Below equations show the maximum level of the input signal in order to keep LVS below threshold (Class D switching on VBAT).

For absolute threshold: Input (dBFS) < LVS_FTH + (21 dBV - ChannelGain [dBV]).

For relative threshold: Input (dBFS) < 20log10 (VBAT1S*CD_EFF - LVS_RTH) + (21 dBV - ChannelGain [dBV]) - 1.5dB.

Where:

* ChannelGain = AMP_LEVEL + DVC_LVL + SAFE_MODE (if enabled, it is -18dB).

* CD_EFF is set by registers 48h-4Bh from page 0x04 and LVH_RTH is set by bits [3:0] of register 6Ah from page 0x00.

* 1.5dB is an inflection factor, already included for absolute threshold.

BOP, Limiter, Thermal Foldback and Thermal Gradient Gain Attenuation should not be taken into account for calculating LV_EN threshold.

Figure 8-5 Low Voltage Signaling (Input=0dB, Gain=0dB)

The group delay numbers are optimized based on whether the Noise Gate feature is enabled or disabled. The delay on CDS_DLY path and LVS_DLY path varies depending on sampling rate and whether Noise Gate mode is enabled or not (see Section 8.9.91).

The LVS fixed thresholds, when CDS_MODE[1:0]=11 (PWR_MODE2 from Section 11.1), can be set using register bits LVS_FTH_LOW[1:0]. When CDS_MODE[1:0]=00 (PWR_MODE1 and PWR_MODE3 from Section 11.1) the thresholds should be set with register bits LVS_FTH[4:0].