An ADC monitors PVDD voltage, VBAT1S voltage and die temperature. The results of these conversions are available via register readback (PVDD_CNV, VBAT1S_CNV and TMP_CNV registers). PVDD and VBAT1S voltage conversions are also used by the limiter and brown out prevention blocks.

When BOP_SRC=1, VBAT1S conversion is not enabled and the ADC monitors only PVDD and temperature.

In order to prevent false triggering of BOP, limiter, thermal foldback, the initial values of SAR at power up are VBAT1S = 6 V, PVDD = 16 V, TEMP = 2.6 ⁰C.

The ADC runs at a rate of 192 kHz with a conversion time of 5.2 μs.

Sampling rate for temperature is 10K samples/sec.

Actual PVDD and VBAT1S voltages are calculated by dividing the PVDD_CNV[11:0] and VBAT1S_CNV[11:0] decimal values of register bits by 128. The die temperature is calculated by subtracting 93 from the decimal value of TMP_CNV[7:0] register bits. The supply voltages PVDD and VBAT1S can be filtered using the proper setting of the SAR_FLT[1:0] register bits but will increase measurement latency. The register bits content should always be read from MSB to LSB.