ZHCSHK8E october   2017  – july 2023 TAS2770

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 PDM Port Timing Requirements
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Mode and Address Selection
      2. 8.3.2 General I2C Operation
      3. 8.3.3 Single-Byte and Multiple-Byte Transfers
      4. 8.3.4 Single-Byte Write
      5. 8.3.5 Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6 Single-Byte Read
      7. 8.3.7 Multiple-Byte Read
      8. 8.3.8 Register Organization
    4. 8.4 Device Functional Modes
      1. 8.4.1  PDM Input
      2. 8.4.2  TDM Port
      3. 8.4.3  Playback Signal Path
        1. 8.4.3.1 High Pass Filter
        2. 8.4.3.2 Digital Volume Control and Amplifier Output Level
        3. 8.4.3.3 Audio Playback Selection
        4. 8.4.3.4 Battery Tracking Limiter with Brown Out Prevention
        5. 8.4.3.5 Inter Chip Limiter Alignment
          1. 8.4.3.5.1 TDM Mode
        6. 8.4.3.6 Class-D Settings
      4. 8.4.4  SAR ADC
      5. 8.4.5  IV Sense
      6. 8.4.6  Clocks and PLL
      7. 8.4.7  Operational Modes
        1. 8.4.7.1 Hardware Shutdown
        2. 8.4.7.2 Software Shutdown
        3. 8.4.7.3 Mute
        4. 8.4.7.4 Active
        5. 8.4.7.5 Mode Control and Software Reset
      8. 8.4.8  Faults and Status
      9. 8.4.9  Power Sequencing Requirements
      10. 8.4.10 Digital Input Pull Downs
    5. 8.5 Register Maps
      1. 8.5.1 Register Summary Table Book=0x00 Page=0x00
      2. 8.5.2 Register Maps
        1. 8.5.2.1  PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
        2. 8.5.2.2  SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
        3. 8.5.2.3  PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
        4. 8.5.2.4  PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
        5. 8.5.2.5  PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
        6. 8.5.2.6  PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
        7. 8.5.2.7  PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
        8. 8.5.2.8  MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
        9. 8.5.2.9  PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
        10. 8.5.2.10 PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
        11. 8.5.2.11 TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
        12. 8.5.2.12 TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
        13. 8.5.2.13 TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
        14. 8.5.2.14 TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
        15. 8.5.2.15 TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
        16. 8.5.2.16 TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
        17. 8.5.2.17 TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
        18. 8.5.2.18 TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
        19. 8.5.2.19 TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
        20. 8.5.2.20 TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
        21. 8.5.2.21 TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
        22. 8.5.2.22 LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
        23. 8.5.2.23 LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
        24. 8.5.2.24 LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
        25. 8.5.2.25 LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
        26. 8.5.2.26 LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
        27. 8.5.2.27 LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
        28. 8.5.2.28 BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
        29. 8.5.2.29 BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
        30. 8.5.2.30 BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
        31. 8.5.2.31 ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
        32. 8.5.2.32 ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
        33. 8.5.2.33 INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
        34. 8.5.2.34 INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
        35. 8.5.2.35 INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
        36. 8.5.2.36 INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
        37. 8.5.2.37 INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
        38. 8.5.2.38 INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
        39. 8.5.2.39 INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
        40. 8.5.2.40 VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
        41. 8.5.2.41 VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
        42. 8.5.2.42 TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
        43. 8.5.2.43 TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
        44. 8.5.2.44 INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
        45. 8.5.2.45 DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
        46. 8.5.2.46 MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
        47. 8.5.2.47 CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
        48. 8.5.2.48 TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
        49. 8.5.2.49 REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
        50. 8.5.2.50 I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
        51. 8.5.2.51 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Overview
        2. 9.2.2.2 Select Input Capacitance
        3. 9.2.2.3 Select Decoupling Capacitors
        4. 9.2.2.4 Select Bootstrap Capacitors
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Initial Device Configuration - Auto Rate
      2. 9.3.2 Initial Device Configuration - 48 kHz
      3. 9.3.3 Initial Device Configuration - 44.1 kHz
      4. 9.3.4 Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5 Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6 Device Mute
      7. 9.3.7 Device Un-Mute
      8. 9.3.8 Device Sleep
      9. 9.3.9 Device Wake
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

8.5.2.31 ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]

ICLA starting time slot and enable.

Figure 8-48 ICLA_CFG0 Register Address: 0x1E
76543210
ICLA_USE_MAXICLA_SLOT[5:0]ICLA_EN
RW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-112 Inter Chip Limiter Alignment 0 Field Descriptions
BitFieldTypeResetDescription
7ICLA_USE_MAXRW0hInter chip limiter alignment min/max config
0b = Use the maximum of the ICLA group gain reduction
1b = Use the minimum of the ICLA group gain reduction
6-1ICLA_SLOT[5:0]RW0hInter chip limiter alignment starting time slot.
0ICLA_ENRW0hInter chip limiter alignment enable.
0b = Disabled
1b = Enabled
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