ZHCSHK8E october 2017 – july 2023 TAS2770
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| DIGITAL INPUT and OUTPUT | ||||||
| VIH | High-level digital input logic voltage threshold | All digital pins except SDA and SCL; IOVDD = 1.8 V. | 0.65 × IOVDD | V | ||
| VIL | Low-level digital input logic voltage threshold | All digital pins except SDA and SCL; IOVDD = 1.8 V. | 0.35 × IOVDD | V | ||
| VIH(I2C) | High-level digital input logic voltage threshold | SDA and SCL; IOVDD = 1.8 V. | 0.7 x IOVDD | V | ||
| VIL(I2C) | Low-level digital input logic voltage threshold | SDA and SCL; IOVDD = 1.8 V. | 0.3 x IOVDD | V | ||
| VOH | High-level digital output voltage | All digital pins except SDA, SCL and IRQZ; IOVDD = 1.8 V; IOH = 2 mA. | IOVDD – 0.45 V | V | ||
| VOL | Low-level digital output voltage | All digital pins except SDA, SCL and IRQZ; IOVDD = 1.8 V; IOL = –2 mA. | 0.45 | V | ||
| VOL(I2C) | Low-level digital output voltage | SDA and SCL; IOVDD = 1.8 V; IOL(I2C) = –2 mA. | 0.2 x IOVDD | V | ||
| VOL(IRQZ) | Low-level digital output voltage for IRQZ open drain Output | IRQZ; IOVDD = 1.8 V; IOL(IRQZ) = –2 mA. | 0.45 | V | ||
| IIH | Input logic-high leakage for digital inputs | All digital pins; Input = IOVDD. | –5 | 0.1 | 5 | µA |
| IIL | Input logic-low leakage for digital inputs | All digital pins; Input = GND. | –5 | 0.1 | 5 | µA |
| CIN | Input capacitance for digital inputs | All digital pins | 5 | pF | ||
| RPD | Pull down resistance for digital input/IO pins when asserted on | SDOUT, SDIN, FSYNC, SBCLK, PDMD, PDMCK | 18 | kΩ | ||
| TDM SERIAL AUDIO PORT | ||||||
| PCM Sample Rates & FSYNC Input Frequency | Single Speed, I2S/TDM Operation | 48 | kHz | |||
| Double Speed, I2S/TDM Operation | 96 | |||||
| Quadruple Speed, I2S/TDM Operation | 192 | |||||
| SBCLK Input Frequency | I2S/TDM Operation | 2.54 | 27.1 | MHz | ||
| SBCLK Maximum Input Jitter | RMS Jitter below 40 kHz that can be tolerated without performance degradation | 1 | ns | |||
| RMS Jitter above 40 kHz that can be tolerated without performance degradation | 10 | |||||
| SBCLK Cycles per FSYNC in I2S and TDM Modes | Values: 64, 96, 128, 192, 256, 384 and 512 | 64 | 512 | Cycles | ||
| PDM AUDIO PORT | ||||||
| PDM clock input frequency | Single Rate PDM | 3.072 | MHz | |||
| Double Rate PDM | 6.144 | |||||
| PDM sensor clock rate to PCM sample rate oversampling ratios | Single Speed PCM. Values: 64X and 128X. | 64 | 128 | |||
| Double Speed PCM. Values: 32X and 64X. | 32 | 64 | ||||
| Quadruple Speed PCM. Values: 16X and 32X. | 16 | 32 | ||||
| PROTECTION CIRCUITRY | ||||||
| Thermal shutdown temperature | 140 | °C | ||||
| Thermal shutdown retry | 1.5 | s | ||||
| VBAT undervoltage lockout threshold (UVLO) | UVLO is asserted | 4 | V | |||
| VBAT overvoltage lockout threshold (OVLO) | OVLO is asserted | 18 | V | |||
| AMPLIFIER PERFORMANCE | ||||||
| POUT | Maximum Continuous Output Power 0.1% THD+N | RL = 8 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 8.4 V | 3.7 | W | ||
| RL = 4 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 8.4 V | 6.6 | |||||
| RL = 8 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 12.6 V | 8.5 | |||||
| RL = 4 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 12.6 V | 14.2 | |||||
| Maximum Continuous Output Power 1% THD+N | RL = 8 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 8.4 V | 4 | ||||
| RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 8.4 V | 7.1 | |||||
| RL = 8 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 12.6 V | 9.1 | |||||
| RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 12.6 V | 15.4 | |||||
| System efficiency at POUT = 1 W | RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 8.4 V | 89 % | ||||
| RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 8.4 V | 84 % | |||||
| RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 12.6 V | 87.5 % | |||||
| RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 12.6 V | 82.7 % | |||||
| System efficiency at 0.1% THD+N power level | RL = 8 Ω + 33 µH, POUT = 3. 7W, fin = 1 kHz, VBAT = 8.4 V | 92 % | ||||
| RL = 4 Ω + 33 µH, POUT = 6.6 W, fin = 1 kHz, VBAT = 8.4 V | 87 % | |||||
| RL = 8 Ω + 33 µH, POUT = 8.5 W, fin = 1 kHz, VBAT = 12.6 V | 92 % | |||||
| RL = 4 Ω + 33 µH, POUT = 14.2 W, fin = 1 kHz, VBAT = 12.6 V | 86 % | |||||
| THD+N | Total harmonic distortion + noise | POUT = 1 W, RL = 8 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 8.4 V | 0.01 % | |||
| POUT = 1 W, RL = 4 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 8.4 V | 0.01 % | |||||
| POUT = 1 W, RL = 8 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 12.6 V | 0.01 % | |||||
| POUT = 1 W, RL = 4 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 12.6 V | 0.01 % | |||||
| VN | Idle channel noise | A-Weighted, 20 Hz - 20 kHz, DAC Modulator Running | 31 | µV | ||
| VBAT = 8.4 V | 32 | µV | ||||
| VBAT = 12.6 V | 36 | µV | ||||
| FPWM | Class-D PWM switching frequency | Average frequency in Spread Spectrum Mode, CLASSD_SYNC=0 | 384 | kHz | ||
| Fixed Frequency Mode, CLASSD_SYNC=0 | 345.6 | 384 | 422.4 | |||
| Fixed Frequency Mode, CLASSD_SYNC=1, fs = 44.1, 88.2, 174.6 kHz | 44.1·8 | |||||
| Fixed Frequency Mode, CLASSD_SYNC=1, fs = 48, 96, 192 kHz | 48·8 | |||||
| VOS | Output offset voltage | -1 | 1 | mV | ||
| DNR | Dynamic range | A-Weighted, -60 dBFS Method | 108 | dB | ||
| SNR | Signal to noise ratio | A-Weighted, Referenced to 1 % THD+N Output Level | 108 | dB | ||
| KCP | Click and pop performance | Into and out of Mute, Shutdown, Power Up, Power Down and audio clocks starting and stopping. A-weighted | 5 | mV | ||
| Programmable output level range | 12.5 | 21 | dBV | |||
| Programmable output level step size | 0.5 | dB | ||||
| AVERROR | Amplifier gain error | POUT=1W | ±0.1 | dB | ||
| ARIPPLE | Frequency response passband ripple | 20 Hz - 20 kHz | ±0.1 | dB | ||
| Mute attenuation | Device in Shutdown or Muted in Normal Operation | 110 | dB | |||
| Output short circuit limit | VBAT = 12.6 V, Output to Output, Output to GND or Output to VBAT Short | 6 | A | |||
| RDS(ON)FET | Power stage on-resistance (high-side + low-side + sense resistor) | TA = 25 °C | 510 | mΩ | ||
| VBAT power-supply rejection ratio | VBAT = 12.6 V + 200 mVpp, fripple = 217 Hz | 105 | dB | |||
| VBAT = 12.6 V + 200 mVpp, fripple = 20 kHz | 86 | |||||
| AVDD power-supply rejection ratio | AVDD = 1.8 V + 200 mVpp, fripple = 217 Hz | 95 | dB | |||
| AVDD = 1.8 V + 200 mVpp, fripple = 20 kHz | 88 | |||||
| Turn on time from release of SW shutdown | No Volume Ramping | 1.2 | ms | |||
| Volume Ramping | 5.3 | |||||
| Turn off time from assertion of SW shutdown to amp Hi-Z | No Volume Ramping | 0.3 | ms | |||
| Volume Ramping | 4.7 | |||||
| PCM PLAYBACK CHARACTERISTICS | ||||||
| Playback latency from latched input sample to speaker terminals | Single Speed, I2S/TDM | 3.5 | samples | |||
| Double Speed, I2S/TDM | 3.5 | |||||
| Quadruple Speed, I2S/TDM | 3.5 | |||||
| Playback –0.1 dB bandwidth | Single Speed, I2S/TDM | 23.06 | kHz | |||
| Double Speed, I2S/TDM | 21.79 | |||||
| Quadruple Speed, I2S/TDM | 21.69 | |||||
| Playback –3 dB bandwidth | Single Speed, I2S/TDM | 24 | kHz | |||
| Double Speed, I2S/TDM | 23 | |||||
| Quadruple Speed, I2S/TDM | 27.26 | |||||
| PDM PLAYBACK CHARACTERISTICS | ||||||
| Playback latency from latched data bit to speaker terminals | Single Rate PDM, PDMD input | 7.07 | µs | |||
| Double Rate PDM, PDMD input | 5.02 | |||||
| Playback –0.1 dB bandwidth | Single Rate PDM, PDMD input | 41.5 | kHz | |||
| Double Rate PDM, PDMD input | 88 | |||||
| Playback –3 dB bandwidth | Single Rate PDM, PDMD input | 77.5 | kHz | |||
| Double Rate PDM, PDMD input | 143 | |||||
| SPEAKER CURRENT SENSE | ||||||
| DNR | Dynamic range | Un-Weighted, Relative to 0 dBFS | 69 | dB | ||
| THD+N | Total harmonic distortion + noise | RL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 5 W | –60 | dB | ||
| RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 7.5 W | –60 | |||||
| Full-scale input current | 3.75 | A | ||||
| Current-sense accuracy | RL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W) | ±1 % | ||||
| Current-sense gain error over temperature | –20°C to 70°C, POUT = 1 W | ±0.75% | ||||
| Current-sense gain error over output power | 50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone | ±0.75% | ||||
| Current-sense frequency response | Max deviation above and below passband gain | ±0.2 | dB | |||
| SPEAKER VOLTAGE SENSE | ||||||
| DNR | Dynamic range | Un-Weighted, Relative 0 dBFS | 69 | dB | ||
| THD+N | Total harmonic distortion + noise | RL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 5 W | –60 | dB | ||
| RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 7.5 W | –60 | |||||
| Full-scale input voltage | 14 | VPK | ||||
| Voltage-sense accuracy | RL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W) | ±1% | ||||
| Voltage-sense gain error over temperature | –20°C to 70°C, POUT = 1 W | ±0.75% | ||||
| Voltage-sense gain error over output power | 50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone | ±0.75% | ||||
| Voltage-sense frequency response | Max deviation above and below passband gain | ±0.2 | dB | |||
| SPEAKER VOLTAGE/CURRENT SENSE RATIO | ||||||
| Gain ratio error over output power | 50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone | ±0.75% | ||||
| Gain ratio error over temperature | –20°C to 70°C | ±0.5% | ||||
| TYPICAL CURRENT CONSUMPTION | ||||||
| Current consumption in hardware shutdown | SDZ = 0, VBAT | 0.1 | µA | |||
| SDZ = 0, AVDD | 1 | |||||
| SDZ = 0, IOVDD | 0.1 | |||||
| Current consumption in software shutdown | All Clocks Stopped, VBAT | 10 | µA | |||
| All Clocks Stopped, AVDD | 10 | |||||
| All Clocks Stopped, IOVDD | 1 | |||||
| Current consumption during active operation with IV sense disabled | fs = 48 kHz, VBAT | 3.1 | mA | |||
| fs = 48 kHz, AVDD | 10 | |||||
| fs = 48 kHz, IOVDD | 0.1 | |||||
| Current consumption during active operation with IV sense enabled | fs = 48 kHz, VBAT | 3.1 | mA | |||
| fs = 48 kHz, AVDD | 12.5 | |||||
| fs = 48 kHz, IOVDD | 0.1 | |||||
| PEAK VOLTAGE LIMITER | ||||||
| Limiter maximum threshold | 2 | 14.7 | V | |||
| Limiter minimum threshold | 2 | 14.7 | V | |||
| Limiter inflection point | 2 | 14.7 | V | |||
| Limiter VBAT tracking slope | 1 | 4 | V/V | |||
| Limiter max attenuation | 1 | 16.5 | dB | |||
| Limiter latency | Time from VBAT dipping below threshold to initial gain reduction | 23 | µs | |||
| Limiter attack rate | 5 | 640 | µs/step | |||
| Limiter attack step size | 0.25 | 2 | dB/step | |||
| Limiter hold time | 0 | 1000 | ms | |||
| Limiter release rate | 10 | 1500 | ms/step | |||
| Limiter release step size | 0.25 | 2 | dB/step | |||
| BROWN OUT PREVENTION LIMITER | ||||||
| Brownout prevention threshold | 4.5 | 10.875 | V | |||
| Brownout prevention threshold step size | 25 | mV | ||||
| Brownout prevention threshold tolerance | Measured at VBAT of 5V and 10V | ±25 | mV | |||
| Brownout prevention latency | Time from VBAT dipping below threshold to initial gain reduction | 20 | µs | |||
| Brownout prevention attack rate | 5 | 640 | µs/step | |||
| Brownout prevention attack step size | 0.5 | 2 | dB/step | |||
| Brownout prevention hold time | 0 | 1000 | ms | |||
| Brownout prevention release rate | 10 | 1500 | ms/step | |||
| Brownout prevention release step size | 0.25 | 2 | dB/step | |||