ZHCSHK8E october   2017  – july 2023 TAS2770

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 PDM Port Timing Requirements
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Mode and Address Selection
      2. 8.3.2 General I2C Operation
      3. 8.3.3 Single-Byte and Multiple-Byte Transfers
      4. 8.3.4 Single-Byte Write
      5. 8.3.5 Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6 Single-Byte Read
      7. 8.3.7 Multiple-Byte Read
      8. 8.3.8 Register Organization
    4. 8.4 Device Functional Modes
      1. 8.4.1  PDM Input
      2. 8.4.2  TDM Port
      3. 8.4.3  Playback Signal Path
        1. 8.4.3.1 High Pass Filter
        2. 8.4.3.2 Digital Volume Control and Amplifier Output Level
        3. 8.4.3.3 Audio Playback Selection
        4. 8.4.3.4 Battery Tracking Limiter with Brown Out Prevention
        5. 8.4.3.5 Inter Chip Limiter Alignment
          1. 8.4.3.5.1 TDM Mode
        6. 8.4.3.6 Class-D Settings
      4. 8.4.4  SAR ADC
      5. 8.4.5  IV Sense
      6. 8.4.6  Clocks and PLL
      7. 8.4.7  Operational Modes
        1. 8.4.7.1 Hardware Shutdown
        2. 8.4.7.2 Software Shutdown
        3. 8.4.7.3 Mute
        4. 8.4.7.4 Active
        5. 8.4.7.5 Mode Control and Software Reset
      8. 8.4.8  Faults and Status
      9. 8.4.9  Power Sequencing Requirements
      10. 8.4.10 Digital Input Pull Downs
    5. 8.5 Register Maps
      1. 8.5.1 Register Summary Table Book=0x00 Page=0x00
      2. 8.5.2 Register Maps
        1. 8.5.2.1  PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
        2. 8.5.2.2  SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
        3. 8.5.2.3  PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
        4. 8.5.2.4  PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
        5. 8.5.2.5  PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
        6. 8.5.2.6  PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
        7. 8.5.2.7  PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
        8. 8.5.2.8  MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
        9. 8.5.2.9  PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
        10. 8.5.2.10 PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
        11. 8.5.2.11 TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
        12. 8.5.2.12 TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
        13. 8.5.2.13 TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
        14. 8.5.2.14 TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
        15. 8.5.2.15 TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
        16. 8.5.2.16 TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
        17. 8.5.2.17 TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
        18. 8.5.2.18 TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
        19. 8.5.2.19 TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
        20. 8.5.2.20 TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
        21. 8.5.2.21 TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
        22. 8.5.2.22 LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
        23. 8.5.2.23 LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
        24. 8.5.2.24 LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
        25. 8.5.2.25 LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
        26. 8.5.2.26 LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
        27. 8.5.2.27 LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
        28. 8.5.2.28 BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
        29. 8.5.2.29 BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
        30. 8.5.2.30 BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
        31. 8.5.2.31 ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
        32. 8.5.2.32 ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
        33. 8.5.2.33 INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
        34. 8.5.2.34 INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
        35. 8.5.2.35 INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
        36. 8.5.2.36 INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
        37. 8.5.2.37 INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
        38. 8.5.2.38 INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
        39. 8.5.2.39 INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
        40. 8.5.2.40 VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
        41. 8.5.2.41 VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
        42. 8.5.2.42 TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
        43. 8.5.2.43 TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
        44. 8.5.2.44 INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
        45. 8.5.2.45 DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
        46. 8.5.2.46 MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
        47. 8.5.2.47 CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
        48. 8.5.2.48 TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
        49. 8.5.2.49 REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
        50. 8.5.2.50 I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
        51. 8.5.2.51 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Overview
        2. 9.2.2.2 Select Input Capacitance
        3. 9.2.2.3 Select Decoupling Capacitors
        4. 9.2.2.4 Select Bootstrap Capacitors
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Initial Device Configuration - Auto Rate
      2. 9.3.2 Initial Device Configuration - 48 kHz
      3. 9.3.3 Initial Device Configuration - 44.1 kHz
      4. 9.3.4 Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5 Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6 Device Mute
      7. 9.3.7 Device Un-Mute
      8. 9.3.8 Device Sleep
      9. 9.3.9 Device Wake
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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6.9 Typical Characteristics

At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for Load Resistance is 30 µH, unless otherwise noted.

GUID-A108584E-0D3F-4EFC-AFB2-26B375C214B6-low.gif
RL = 4 ΩFIN = 1 kHz
Figure 6-1 THD+N vs Output Power
GUID-93197EC0-EB42-45C6-A5A0-CACC9E500EA7-low.gif
RL = 4 ΩFIN = 6.667 kHz
Figure 6-3 THD+N vs Output Power
GUID-5355D8EF-C2E5-42D1-8C1D-0810E5348EB7-low.gif
FIN = 20 Hz – 20 kHzPOUT = 0.1 WRL = 4 Ω + 30 µH
Figure 6-5 THD+N vs Frequency
GUID-115E1D75-9CA9-461F-9587-6B0EA0203BFC-low.gif
FIN = 20 Hz – 20 kHzPOUT = 5 WRL = 4 Ω + 30 µH
Figure 6-7 THD+N vs Frequency
GUID-0645C13C-5535-4AFA-9AAD-47427E2B37DE-low.gif
VBAT = 4.5 V – 16 V
Figure 6-9 Idle Channel Noise (A-Weighted) vs VBAT
GUID-244D2E02-78E5-49B6-A654-8E152F3C5C32-low.gif
RL = 4 Ω
Figure 6-11 Max Output Power vs THD+N
GUID-F34D6B8F-B263-4714-8CB3-D9006F1625DE-low.gif
RL = 4 ΩFIN = 1 kHz
Figure 6-13 Efficiency vs Output Power
GUID-40EA2CB2-11D3-4BFD-9233-4C9E1E7E3E56-low.gif
Figure 6-15 VDD PSRR vs Frequency
GUID-CA06CC96-1D49-4E29-A8BC-B8EDBDBC0B53-low.gif
VBAT = 4.5 V – 16 V
Figure 6-17 VBAT Idle Current vs VBAT
GUID-BDA7C253-14D0-4DAD-937F-8617F95C2394-low.gif
RL = 4 ΩFIN = 1 kHz
Figure 6-19 ISENSE THD+N vs Output Power
GUID-375CA2AF-261E-43FE-BB5E-426D0593BD3D-low.gif
RL = 4 ΩPilot tone = 40 Hz, 34 dB
Figure 6-21 ISENSE Gain Linearity vs Output Power
GUID-624E176D-7599-4805-AF27-FBB3B29CBDD8-low.gif
FIN = 20 Hz – 20 kHzPOUT = 1 W
Figure 6-23 ISENSE THD+N vs Frequency
GUID-4FFF4A9B-22A0-47DC-805A-A623A37FB4AE-low.gif
RL = 8 Ω
Figure 6-25 VSENSE THD+N vs Output Power
GUID-95B490E5-3376-4A6B-BC07-F081E557E206-low.gif
FIN = 20 Hz – 20 kHzPOUT = 1 W
Figure 6-27 VSENSE THD+N vs Frequency
GUID-477A4110-160B-4089-8FC5-BA55ED669B09-low.gif
RL = 4 Ω + 30 µHPilot tone = 40 Hz, 34 dB
Figure 6-29 V/ISENSE Gain Linearity vs Output Power
GUID-EAE5C965-123C-46D1-BC91-6F1D7FC1665C-low.gif
TA = –20°C – 70°CPilot tone = 40 Hz, 34 dB
Figure 6-31 VSENSE Gain Deviation vs Temperature
GUID-DD48EFBA-A394-4780-9195-0EF55F13E974-low.gif
RL = 8 ΩFS = 1 kHzFIN = 1 kHz
Figure 6-2 THD+N vs Output Power
GUID-E16F36F7-70EF-4F76-A655-10AB0A069293-low.gif
RL = 8 ΩFIN = 6.667 kHz
Figure 6-4 THD+N vs Output Power
GUID-3B5DF6F9-C681-4377-8E2F-624790C5EFCD-low.gif
FIN = 20 Hz – 20 kHzPOUT = 1 WRL = 4 Ω + 30 µH
Figure 6-6 THD+N vs Frequency
GUID-FD7FCD6B-E469-4756-81F0-8F39FC953409-low.gif
FIN = 20 Hz – 20 kHzPOUT = 1 WRL = 8 Ω + 30 µH
Figure 6-8 THD+N vs Frequency
GUID-C22681F2-20D3-465E-A854-972427B45990-low.gif
FS = 48 kHzPOUT = 1 W
Figure 6-10 Amplitude vs Frequency
GUID-3919073B-959A-44B9-A618-C44CFF5E4E08-low.gif
RL = 8 Ω
Figure 6-12 Max Output Power vs THD+N
GUID-1931C8AC-C610-4D98-9A07-F1ADE335AFE5-low.gif
RL = 8 ΩFIN = 1 kHz
Figure 6-14 Efficiency vs Output Power
GUID-D8D46D24-1E22-42D5-BE3E-59194B80D93A-low.gif
Figure 6-16 VBAT PSRR vs Frequency
GUID-BF4F64E6-D095-4127-A914-CBAB90243058-low.gif
A.
AVDD = 1.65 V – 1.95 VIV Sense Enabled
Figure 6-18 AVDD Idle Current vs AVDD
GUID-29817B7F-760C-4E88-AD8A-D92A6131B48F-low.gif
RL = 8 ΩFIN = 1 kHz
Figure 6-20 ISENSE THD+N vs Output Power
GUID-1068790C-2A41-4933-AD41-D90F7E44364A-low.gif
FIN = 20 Hz – 20 kHzPOUT = 1 W
Figure 6-22 ISENSE THD+N vs Frequency
GUID-B43E0177-6112-485C-AA6E-CDAF5E618C3C-low.gif
RL = 4 Ω
Figure 6-24 VSENSE THD+N vs Output Power
GUID-8CE01F4A-AFE5-49FA-9766-ED0101F92FCA-low.gif
RL = 4 ΩPilot tone = 40 Hz, 34 dB
Figure 6-26 Output Power vs VSENSE Linearity
GUID-F5A0AEDF-AE52-42CB-934E-FB93DC750CB7-low.gif
FIN = 20 Hz – 20 kHzPOUT = 1 W
Figure 6-28 VSENSE THD+N vs Frequency
GUID-17CB8624-1175-4BCA-922B-39FB9752AF68-low.gif
TA = –20°C – 70°CPilot tone = 40 Hz, 34 dB
Figure 6-30 ISENSE Gain Deviation vs Temperature
GUID-83345C17-B68B-41CB-BB7B-654948E51748-low.gif
TA = –20°C – 70°CPilot tone = 40 Hz, 34 dB
Figure 6-32 V/ISENSE Gain Deviation vs Temperature
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