ZHCSHK8E october 2017 – july 2023 TAS2770
PRODUCTION DATA
Sets TDM TX bus keeper, fill, offset and transmit edge.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TX_LSB_CFG | TX_KEEPER_CFG | TX_KEEPER | TX_FILL | TX_OFFSET[2:0] | TX_EDGE | ||
| RW-0h | RW-0h | RW-0h | RW-1h | RW-1h | RW-1h | ||
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | TX_LSB_CFG | RW | 0h | TDM TX SDOUT LSB data option 0b = TX SDOUT LSB is driven for full-cycle (provided TX_KEEPER is '0') 1b = TX SDOUT LSB is driven for half-cycle |
| 6 | TX_KEEPER_CFG | RW | 0h | TDM TX SDOUT bus keeper configuration. 0b = Bus keeper is enabled only for 1 LSB bit cycle & SDOUT LSB driven for half cycle (provided TX_KEEPER is '1') 1b = Bus keeper is always enabled & SDOUT LSB driven for half cycle (provided TX_KEEPER is '1') |
| 5 | TX_KEEPER | RW | 0h | TDM TX SDOUT bus keeper enable. 0b = Disable bus keeper 1b = Enable bus keeper |
| 4 | TX_FILL | RW | 1h | TDM TX SDOUT unused bitfield fill. 0b = Transmit 0 1b = Transmit Hi-Z |
| 3-1 | TX_OFFSET[2:0] | RW | 1h | TDM TX start of frame to time slot 0 offset. |
| 0 | TX_EDGE | RW | 1h | TDM TX launch clock polarity. 0b = Rising edge of SBCLK 1b = Falling edge of SBCLK |