米6体育平台手机版

ZHCSIA0A May 2018 – November 2018 TAS3251

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DKQ|56
- MPDS378A

散热焊盘机械数据 (封装 | 引脚)

DKQ|56
- PPTD343

订购信息

zhcsia0a_oa

7.6 DAC Electrical Characteristics

Free-air room temperature 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
DIGITAL I/O
V_IH1	Input logic high threshold for DAC_DVDD referenced digital inputs⁽¹⁾		70%		V_{DAC_DVDD}
V_IL1	Input logic low threshold for DAC_DVDD referenced digital inputs⁽¹⁾			30%	V_{DAC_DVDD}
I_IH1	Input logic high current level for DAC_DVDD referenced digital input pins⁽¹⁾	V_IN(DigIn) = V_{DAC_DVDD}		10	µA
I_IL1	Input logic low current level for DAC_DVDD referenced digital input pins⁽¹⁾	V_IN(DigIn)= 0 V		–10	µA
V_OH(DigOut)	Output logic high voltage level⁽¹⁾	I_OH = 4 mA	80%		V_{DAC_DVDD}
V_OL(DigOut)	Output logic low voltage level⁽¹⁾	I_OH = –4 mA		22%	V_{DAC_DVDD}
I²C CONTROL PORT
C_L(I2C)	Allowable load capacitance for each I²C Line			400	pF
f_SCL(fast)	Support SCL frequency	No wait states, fast mode		400	kHz
f_SCL(slow)	Support SCL frequency	No wait states, slow mode		100	kHz
V_NH	Noise margin at High level for each connected device (including hysteresis)		0.2 × V_{DAC_DVDD}		V
MCLK AND PLL SPECIFICATIONS
D_MCLK	Allowable MCLK duty cycle		40%	60%
f_MCLK	Supported MCLK frequencies	Up to 50 MHz	128	512	f_S⁽²⁾
f_PLL	PLL input frequency	Clock divider uses fractional divide D > 0, P = 1	6.7	20	MHz
f_PLL	PLL input frequency	Clock divider uses integer divide D = 0, P = 1	1	20	MHz
SERIAL AUDIO PORT
t_DLY	Required LRCK/FS to SCLK rising edge delay		5		ns
D_SCLK	Allowable SCLK duty cycle		40%	60%
f_S	Supported input sample rates		8	96	kHz
f_SCLK	Supported SCLK frequencies		32	64	f_S⁽²⁾
f_SCLK	SCLK frequency	Either master mode or slave mode		24.576	MHz

(1) DAC_DVDD referenced digital pins include: ADR, LRCK, MCLK, DAC_MUTE, SCL, SCLK, SDA, SDIN, SDOUT and XPU.

(2) A unit of f_S indicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the TAS3251 device.