8.3.4.4.1 Data Formats and Master/Slave Modes of Operation

The TAS3251 device supports industry-standard audio data formats, including standard I²S and left-justified. Data formats are selected via Register (P0-R40). All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. The data formats are detailed in Figure 24 through Figure 29.

The TAS3251 device also supports right-justified and TDM/DSP data. I²S, LJ, RJ, and TDM/DSP are selected using Register (P0-R40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are accepted. Default setting is I²S and 24 bit word length. The I²S slave timing is shown in Figure 3.

shows a detailed timing diagram for the serial audio interface.

In addition to acting as a I²S slave, the TAS3251 device can act as an I²S master, by generating SCLK and LRCK/FS as outputs from the MCLK input. Table 9 lists the registers used to place the device into Master or Slave mode. Please refer to theSerial Audio Port Timing – Master Mode section for serial audio Interface timing requirements in Master Mode. For Slave Mode timing, please refer to to the Serial Audio Port Timing – Slave Mode section.

Figure 24. Left Justified Audio Data Format

I²S Data Format; L-channel = LOW, R-channel = HIGH

Figure 25. I²S Audio Data Format

Right Justified Data Format; L-channel = HIGH, R-channel = LOW

Figure 26. Right Justified Audio Data Format

TDM/DSP Data Format with OFFSET = 0

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 27. TDM/DSP 1 Audio Data Format

TDM/DSP Data Format with OFFSET = 1

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 28. TDM/DSP 2 Audio Data Format

TDM/DSP Data Format with OFFSET = N

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 29. TDM/DSP 3 Audio Data Format