ZHCSB67B April   2013  – April 2015 TAS5558

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Dynamic Performance
    7. 6.7  SRC Performance
    8. 6.8  Timing I2C Serial Control Port Operation
    9. 6.9  Reset Timing (RESET)
    10. 6.10 Power-Down (PDN) Timing
    11. 6.11 Back-End Error (BKND_ERR)
    12. 6.12 Mute Timing (MUTE)
    13. 6.13 Headphone Select (HP_SEL)
    14. 6.14 Switching Characteristics - Clock Signals
    15. 6.15 Switching Characteristics - Serial Audio Port
    16. 6.16 Volume Control
    17. 6.17 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Audio Interface Control and Timing
        1. 7.3.1.1 Input I2S Timing
        2. 7.3.1.2 Left-Justified Timing
        3. 7.3.1.3 Right-Justified Timing
      2. 7.3.2 OUTPUT Serial Audio Output
      3. 7.3.3 I2S Master Mode
      4. 7.3.4 LRCKO and SCLKO
      5. 7.3.5 PWM Features
        1. 7.3.5.1 DC Blocking (High-Pass Filter Enable/Disable)
        2. 7.3.5.2 AM Interference Avoidance
      6. 7.3.6 TAS5558 Controls and Status
        1. 7.3.6.1 I2C Status Registers
          1. 7.3.6.1.1 General Status Register (0x01)
          2. 7.3.6.1.2 Error Status Register (0x02)
        2. 7.3.6.2 TAS5558 Pin Controls
          1. 7.3.6.2.1 Reset (RESET)
          2. 7.3.6.2.2 Power Down (PDN)
          3. 7.3.6.2.3 Back-End Error (BKND_ERR)
            1. 7.3.6.2.3.1 BKND_ERR and VALID
          4. 7.3.6.2.4 Speaker/Headphone Selector (HP_SEL)
          5. 7.3.6.2.5 Mute (MUTE)
          6. 7.3.6.2.6 Power-Supply Volume Control (PSVC)
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Supply
      2. 7.4.2  Clock, PLL, and Serial Data Interface
      3. 7.4.3  Serial Audio Interface
      4. 7.4.4  I 2C Serial-Control Interface
      5. 7.4.5  Device Control
      6. 7.4.6  Energy Manager
      7. 7.4.7  Digital Audio Processor (DAP)
        1. 7.4.7.1 TAS5558 Audio-Processing Configurations
        2. 7.4.7.2 TAS5558 Audio-Processing Feature Sets
      8. 7.4.8  Pulse Width Modulation Schemes
      9. 7.4.9  TAS5558 DAP Architecture Diagrams
      10. 7.4.10 I 2C Coefficient Number Formats
        1. 7.4.10.1 Digital Audio Processor (DAP) Arithmetic Unit
        2. 7.4.10.2 28-Bit 5.23 Number Format
        3. 7.4.10.3 TAS5558 Audio Processing
      11. 7.4.11 Input Crossbar Mixer
      12. 7.4.12 Biquad Filters
      13. 7.4.13 Bass and Treble Controls
      14. 7.4.14 Volume, Automute, and Mute
      15. 7.4.15 Loudness Compensation
        1. 7.4.15.1 Loudness Example
      16. 7.4.16 Dynamic Range Control (DRC)
        1. 7.4.16.1 DRC Implementation
        2. 7.4.16.2 Compression/Expansion Coefficient Computation Engine Parameters
          1. 7.4.16.2.1 Threshold Parameter Computation
          2. 7.4.16.2.2 Offset Parameter Computation
          3. 7.4.16.2.3 Slope Parameter Computation
      17. 7.4.17 THD Manager
      18. 7.4.18 Downmix Algorithm and I2S Out
      19. 7.4.19 Stereo Downmixes/(or Fold-Downs)
        1. 7.4.19.1 Left Total/Right Total (Lt/Rt)
        2. 7.4.19.2 Left Only/Right Only (Lo/Ro)
      20. 7.4.20 Output Mixer
      21. 7.4.21 Device Configuration Controls
        1. 7.4.21.1 Channel Configuration
        2. 7.4.21.2 Headphone Configuration Registers
        3. 7.4.21.3 Audio System Configurations
          1. 7.4.21.3.1 Using Line Outputs in 6-Channel Configurations
        4. 7.4.21.4 Recovery from Clock Error
        5. 7.4.21.5 Power-Supply Volume-Control Enable
        6. 7.4.21.6 Volume and Mute Update Rate
        7. 7.4.21.7 Modulation Index Limit
      22. 7.4.22 Master Clock and Serial Data Rate Controls
        1. 7.4.22.1 192kHz Native Processing Mode
        2. 7.4.22.2 Supported MCLK Frequencies on the TAS5558
        3. 7.4.22.3 PLL Operation
        4. 7.4.22.4 MCLK Ratio Auto Detection
      23. 7.4.23 Bank Controls (ASRC Bypass only)
        1. 7.4.23.1 Manual Bank Selection
        2. 7.4.23.2 Automatic Bank Selection
          1. 7.4.23.2.1 Coefficient Write Operations While Automatic Bank Switch Is Enabled
        3. 7.4.23.3 Bank Set
        4. 7.4.23.4 Bank-Switch Timeline
        5. 7.4.23.5 Bank-Switching Example 1
    5. 7.5 Programming
      1. 7.5.1 I2C Serial-Control Interface (Slave Addresses 0x36)
        1. 7.5.1.1 General I2C Operation
        2. 7.5.1.2 Single- and Multiple-Byte Transfers
        3. 7.5.1.3 Single-Byte Write
        4. 7.5.1.4 Multiple-Byte Write
        5. 7.5.1.5 Incremental Multiple-Byte Write
        6. 7.5.1.6 Single-Byte Read
        7. 7.5.1.7 Multiple-Byte Read
    6. 7.6 Register Maps
      1. 7.6.1 Serial-Control I2C Register Summary
      2. 7.6.2 Serial-Control Interface Register Definitions
        1. 7.6.2.1  Clock Control Register (0x00)
        2. 7.6.2.2  General Status Register 0 (0x01)
        3. 7.6.2.3  Error Status Register (0x02)
        4. 7.6.2.4  System Control Register 1 (0x03)
        5. 7.6.2.5  System Control Register 2 (0x04)
        6. 7.6.2.6  Channel Configuration Control Registers (0x05-0x0C)
        7. 7.6.2.7  Headphone Configuration Control Register (0x0D)
        8. 7.6.2.8  Serial Data Interface Control Register (0x0E)
        9. 7.6.2.9  Soft Mute Register (0x0F)
        10. 7.6.2.10 Energy Manager Status Register (0x10)
        11. 7.6.2.11 Automute Control Register (0x14)
        12. 7.6.2.12 Output Automute PWM Threshold and Back-End Reset Period Register (0x15)
        13. 7.6.2.13 Modulation Index Limit Register (0x16, 0x17, 0x18, 0x19)
        14. 7.6.2.14 AD Mode - 8 Interchannel Channel Delay and Global Offset Registers (0x1B to 0x23)
        15. 7.6.2.15 Special Low Z and Mid Z Ramp/Stop Period (0x24)
        16. 7.6.2.16 PWM and EMO Control Register (0x25)
        17. 7.6.2.17 Individual Channel Shutdown (0x27)
        18. 7.6.2.18 Input Mux Registers (0x30, 0x31, 0x32, 0x33)
        19. 7.6.2.19 PWM Mux Registers (0x34, 0x35, 0x36, 0x37)
        20. 7.6.2.20 BD Mode and Ternary - 8 Interchannel Channel Delay (0x38 to 0x3F)
        21. 7.6.2.21 Bank-Switching Command Register (0x40) (TAS5558 + ASRC Bypass)
        22. 7.6.2.22 Input Mixer Registers, Channels 1-8 (0x41-0x48)
        23. 7.6.2.23 Bass Mixer Registers (0x49-0x50)
        24. 7.6.2.24 Biquad Filter Register (0x51-0x88)
        25. 7.6.2.25 Bass and Treble Register, Channels 1-8 (0x89-0x90)
        26. 7.6.2.26 Loudness Registers (0x91-0x95)
        27. 7.6.2.27 DRC1 Control Register CH1-7 (0x96) - Write
        28. 7.6.2.28 DRC2 Control Register CH8 (0x97) - Write Register
        29. 7.6.2.29 DRC1 Data Registers (0x98-0x9C)
        30. 7.6.2.30 DRC2 Data Registers (0x9D-0xA1)
        31. 7.6.2.31 DRC Bypass Registers (0xA2-0xA9)
        32. 7.6.2.32 Output Select and Mix Registers 8x2 (0x-0xAF)
        33. 7.6.2.33 8×3 Output Mixer Registers (0xB0-0xB1)
        34. 7.6.2.34 ASRC Registers (0xC3-C5)
        35. 7.6.2.35 Auto Mute Behavior (0xCC)
        36. 7.6.2.36 PSVC Volume Biquad Register (0xCF)
        37. 7.6.2.37 Volume, Treble, and Bass Slew Rates Register (0xD0)
        38. 7.6.2.38 Volume Registers (0xD1-0xD9)
        39. 7.6.2.39 Bass Filter Set Register (0xDA)
        40. 7.6.2.40 Bass Filter Index Register (0xDB)
        41. 7.6.2.41 Treble Filter Set Register (0xDC)
        42. 7.6.2.42 Treble Filter Index (0xDD)
        43. 7.6.2.43 AM Mode Register (0xDE)
        44. 7.6.2.44 PSVC Range Register (0xDF)
        45. 7.6.2.45 General Control Register (0xE0)
        46. 7.6.2.46 96kHz Dolby Downmix Coefficients (0xE3 to 0xE8)
        47. 7.6.2.47 THD Manager Configuration (0xE9 and 0xEA)
        48. 7.6.2.48 SDIN5 Input Mixer (0xEC-0xF3)
        49. 7.6.2.49 192kHZ Process Flow Output Mixer (0xF4-0xF7)
        50. 7.6.2.50 192kHz Dolby Downmix Coefficients (0xFB and 0xFC)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TAS5558 DVD Receiver Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Serial Port Master/Slave Configurations
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Device System Diagrams
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 Do’s and Don’ts
      1. 8.3.1 Frequency Scaling AM Avoidance
    4. 8.4 Initialization Set Up
      1. 8.4.1 Startup Register Writes to get Audio Functioning
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply
    2. 9.2 Energy Manager
    3. 9.3 Programming Energy Manager
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Power Supply Recommendations

9.1 Power Supply

The TAS5558 requires a single 3.3-V nominal supply for pins DVDD1, DVDD2, AVDD, and AVDD_PWM. The decoupling capacitors for the power supplies should be placed close to the device terminals.

9.2 Energy Manager

TAS5558 has an Energy Manager that can be used to monitor/control the overall energy in the system. The key features are:

  1. There are separate controllers for Satellite (EMO1) and Sub (EMO2) channels. If EMO2 is not enabled, then the EMO1 pin is OR'd with the output of the subwoofer comparator.
  2. The satellite channels participating in the energy estimation are selectable. For example, in the 5.1 Mode, the line out channels can be programmed to not participate in the energy estimation.
  3. There is a mixer for each channel before mixing. This is for scaling each channel before adding. The energy of all participating satellite channels are added and compared with a programmable threshold. If the value crosses the threshold, the satellite_over_power bit in the status register is set. Similarly, if the overall energy is lower than another programmable register, the satellite_idle bit in the status register is set. Both these bits are “sticky,” meaning once set, the external controller has to write a “0” to clear the bit
  4. Similar to the satellite channel, the sub channel energy is also estimated and compared against an upper and lower threshold. If above the upper threshold, the sub_over_power bit is set and if below the threshold, the sub_idle_bit are set. These are also "sticky" bits. Sub channels also have a disable pin that bypass energy comparison.
  5. An OR of the 4 status bits are available on EMO pin

External controller on the detection of EMO interrupt (pin going high) can read the status register for more information.

The controller can shutdown the PWM for idle mode and or reduce channel energy to reduce overall power. The Controller discerns more details on the EMO condition by using the status and enable bits. Figure 52 shows the EMO system for satellite channels. A similar EMO system for the subwoofer channel also will be implemented. The EMO pin is shared between satellite and sub channels.

TAS5558 en_mgr_les270.gifFigure 52. Energy Manager

9.3 Programming Energy Manager

Energy Manager related registers are 0xBA to 0xBE. 0xB2 is a 16 byte averaging filter (alpha filter) for both satellite and sub channel. The scaling coefficients are 0xB3 to 0xBA that multiplies energy of each channel with a scaling factor. The threshold registers are (0xBB, 0xBC, 0xBD and 0xBE) and 0x10 for the results register.

Table 91. Energy Manager Status Register (x10)

D3 D2 D1 D0 FUNCTION
– – – 0/1 Energy below the low threshold for satellite channels
– – 0/1 – Energy above the high threshold for satellite channels
– 0/1 – – Energy below the low threshold for sub-woofer channel
0/1 – – – Energy above the high threshold for sub-woofer channels

Provision to read the whole byte and a way to clear the 4 LSBs (one by one).
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