ZHCS929A May 2012 – March 2015 TAS5622A
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagrams
- 7.3
Feature Description
- 7.3.1 System Power-Up and Power-Down Sequence
- 7.3.2 Start-up and Shutdown Ramp Sequence
- 7.3.3 Unused Output Channels
- 7.3.4 Device Protection System
- 7.3.5 Pin-to-Pin Short Circuit Protection (PPSC)
- 7.3.6 Overtemperature Protection
- 7.3.7 Overtemperature Warning, OTW
- 7.3.8 Undervoltage Protection (UVP) and Power-On Reset (POR)
- 7.3.9 Error Reporting
- 7.3.10 Fault Handling
- 7.3.11 Device Reset
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
- 12机械封装和可订购信息
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VDD to GND, GVDD_X(2) to GND | –0.3 | 13.2 | V | |
| PVDD_X(2) to GND(3), OUT_X to GND(3), BST_X to GVDD_X(2)(3) | –0.3 | 50 | V | |
| BST_X to GND(3)(4) | –0.3 | 62.5 | V | |
| DVDD to GND | –0.3 | 4.2 | V | |
| AVDD to GND | –0.3 | 8.5 | V | |
| OC_ADJ, M1, M2, M3, C_START, INPUT_X to GND | –0.3 | 4.2 | V | |
| RESET, FAULT, OTW, CLIP, to GND | –0.3 | 4.2 | V | |
| Maximum continuous sink current (FAULT, OTW, CLIP) | 9 | mA | ||
| Maximum operating junction temperature, TJ | 0 | 150 | °C | |
| Lead temperature | 260 | °C | ||
| Storage temperature, Tstg | –40 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) GVDD_X and PVDD_X represents a full bridge gate drive or power supply. GVDD_X is GVDD_AB or GVDD_CD, PVDD_X is PVDD_AB or PVDD_CD
(3) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
(4) Maximum BST_X to GND voltage is the sum of maximum PVDD to GND and GVDD to GND voltages minus a diode drop.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | ||||
|---|---|---|---|---|---|---|---|
| PVDD_X | Full-bridge supply | DC supply voltage | 12 | 32.5 | 34 | V | |
| GVDD_X | Supply for logic regulators and gate-drive circuitry | DC supply voltage | 10.8 | 12 | 13.2 | V | |
| VDD | Digital regulator supply voltage | DC supply voltage | 10.8 | 12 | 13.2 | V | |
| RL | Load impedance | BTL | Output filter: L = 10 uH, 1 µF. Output AD modulation, switching frequency > 350 kHz. |
2.5 | 4.0 | Ω | |
| SE | 1.5 | 3.0 | |||||
| PBTL | 1.5 | 2.0 | |||||
| LOUTPUT | Output filter inductance | Minimum inductance at overcurrent limit, including inductor tolerance, temperature and possible inductor saturation | 5 | μH | |||
| FPWM | PWM frame rate | 352 | 384 | 500 | kHz | ||
| CPVDD | PVDD close decoupling capacitors | 0.44 | 1 | μF | |||
| C_START | Start-up ramp capacitor | BTL and PBTL configuration | 100 | nF | |||
| SE and 1xBTL+2xSE configuration | 1 | μF | |||||
| ROC | Overcurrent programming resistor | Resistor tolerance = 5% | 24 | 33 | kΩ | ||
| ROC_LATCHED | Overcurrent programming resistor | Resistor tolerance = 5% | 47 | 62 | 68 | kΩ | |
| TJ | Junction temperature | 0 | 125 | °C | |||
6.4 Thermal Information
| THERMAL METRIC(1) | TAS5622A | UNIT | |
|---|---|---|---|
| DDV (HTSSOP) | |||
| 44 PINS | |||
| RθJH | Junction-to-heat sink thermal resistance | 1.9 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 0.6 | |
| RθJB | Junction-to-board thermal resistance | 1.7 | |
| ψJT | Junction-to-top characterization parameter | 0.6 | |
| ψJB | Junction-to-board characterization parameter | 1.7 | |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
PVDD_X = 32.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION | ||||||
| DVDD | Voltage regulator, only used as a reference node | VDD = 12 V | 3.0 | 3.3 | 3.6 | V |
| AVDD | Voltage regulator, only used as a reference node | VDD = 12 V | 7.8 | V | ||
| IVDD | VDD supply current | Operating, 50% duty cycle | 20 | mA | ||
| Idle, reset mode | 20 | |||||
| IGVDD_X | Gate-supply current per full-bridge | 50% duty cycle | 12 | mA | ||
| Reset mode | 3 | |||||
| IPVDD_X | Full-bridge idle current | 50% duty cycle without load | 12 | mA | ||
| RESET low | 1.7 | |||||
| VDD and GVDD_X at 0V | 0.35 | |||||
| OUTPUT-STAGE MOSFETs | ||||||
| RDS(on), LS | Drain-to-source resistance, low side (LS) | TJ = 25°C, excludes metallization resistance, GVDD = 12 V |
40 | mΩ | ||
| RDS(on), HS | Drain-to-source resistance, high side (HS) | 40 | mΩ | |||
| I/O PROTECTION | ||||||
| Vuvp,GVDD | Undervoltage protection limit, GVDD_X | 8.5 | V | |||
| Vuvp,GVDD, hyst(1) | 0.7 | V | ||||
| Vuvp,VDD | Undervoltage protection limit, VDD | 8.5 | V | |||
| Vuvp,VDD, hyst(1) | 0.7 | V | ||||
| Vuvp,PVDD | Undervoltage protection limit, PVDD_X | 8.5 | V | |||
| Vuvp,PVDD,hyst(1) | 0.7 | V | ||||
| OTW(1) | Overtemperature warning | 115 | 125 | 135 | °C | |
| OTWhyst(1) | Temperature drop needed below OTW temperature for OTW to be inactive after OTW event. | 25 | °C | |||
| OTE(1) | Overtemperature error | 145 | 155 | 165 | °C | |
| OTE-OTWdifferential(1) | OTE-OTW differential | 30 | °C | |||
| OTEHYST(1) | A device reset is needed to clear FAULT after an OTE event | 25 | °C | |||
| OLPC | Overload protection counter | fPWM = 384 kHz | 2.6 | ms | ||
| IOC | Overcurrent limit protection | Resistor – programmable, nominal peak current in 1Ω load, ROC = 24 kΩ | 15 | A | ||
| IOC_LATCHED | Overcurrent limit protection, latched | Resistor – programmable, nominal peak current in 1Ω load, ROC = 62 kΩ | 15 | A | ||
| IOCT | Overcurrent response time | Time from application of short condition to Hi-Z of affected half bridge | 150 | ns | ||
| IPD | Internal pulldown resistor at output of each half bridge | Connected when RESET is active to provide bootstrap charge. Not used in SE mode. | 3 | mA | ||
| STATIC DIGITAL SPECIFICATIONS | ||||||
| VIH | High level input voltage | INPUT_X, M1, M2, M3, RESET | 1.9 | V | ||
| VIL | Low level input voltage | 0.8 | V | |||
| LEAKAGE | Input leakage current | 100 | μA | |||
| OTW / SHUTDOWN (FAULT) | ||||||
| RINT_PU | Internal pullup resistance, OTW, CLIP, FAULT to DVDD | 20 | 26 | 33 | kΩ | |
| VOH | High level output voltage | Internal pullup resistor | 3 | 3.3 | 3.6 | V |
| VOL | Low level output voltage | IO = 4mA | 200 | 500 | mV | |
| FANOUT | Device fanout OTW, FAULT, CLIP | No external pullup | 30 | devices | ||
(1) Specified by design.
6.6 Audio Specification Stereo (BTL)
Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and a TAS5622A power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C,Output Filter: LDEM = 10 μH, CDEM = 1 µF, unless otherwise noted.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| PO | Power output per channel | RL = 3 Ω, 10% THD+N | 150 | W | ||
| RL = 4 Ω, 10% THD+N | 125 | |||||
| RL = 3 Ω, 1% THD+N | 140 | |||||
| RL = 4 Ω, 1% THD+N | 105 | |||||
| THD+N | Total harmonic distortion + noise | 1 W, 1 kHz signal | 0.025% | |||
| Vn | Output integrated noise | A-weighted, AES17 measuring filter | 180 | μV | ||
| VOS | Output offset voltage | No signal | 10 | 20 | mV | |
| SNR | Signal-to-noise ratio(1) | A-weighted, AES17 measuring filter | 105 | dB | ||
| DNR | Dynamic range | A-weighted, –60 dBFS (rel 1% THD+N) | 105 | dB | ||
| Pidle | Power dissipation due to Idle losses (IPVDD_X) | PO = 0, channels switching(2) | 0.8 | W | ||
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
6.7 Audio Specification 4 Channels (SE)
Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and a TAS5622A power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C,Output Filter: LDEM = 10 μH, CDEM = 1 µF, CDCB = 470 µF, unless otherwise noted.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| PO | Power output per channel | RL = 3 Ω, 10% THD+N | 43 | W | ||
| RL = 3 Ω, 1% THD+N | 35 | |||||
| THD+N | Total harmonic distortion + noise | 1 W, 1 kHz signal | 0.025% | |||
| Vn | Output integrated noise | A-weighted, AES17 measuring filter | 180 | μV | ||
| SNR | Signal-to-noise ratio(1) | A-weighted, AES17 measuring filter | 102 | dB | ||
| DNR | Dynamic range | A-weighted, –60 dBFS (rel 1% THD+N) | 102 | dB | ||
| Pidle | Power dissipation due to Idle losses (IPVDD_X) | PO = 0, channels switching(2) | 0.8 | W | ||
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
6.8 Audio Specification Mono (PBTL)
Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and a TAS5622A power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 μF, unless otherwise noted.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| PO | Power output per channel | RL = 1.5 Ω, 10%, THD+N | 330 | W | ||
| RL = 2 Ω, 10% THD+N | 250 | |||||
| RL = 4 Ω, 10% THD+N | 130 | |||||
| RL = 1.5 Ω, 1% THD+N | 270 | |||||
| RL = 2 Ω, 1% THD+N | 210 | |||||
| RL = 4 Ω, 1% THD+N | 105 | |||||
| THD+N | Total harmonic distortion + noise | 1 W, 1 kHz signal | 0.025% | |||
| Vn | Output integrated noise | A-weighted, AES17 measuring filter | 180 | μV | ||
| VOS | Output offset voltage | No signal | 10 | 20 | mV | |
| SNR | Signal to noise ratio(1) | A-weighted, AES17 measuring filter | 105 | dB | ||
| DNR | Dynamic range | A-weighted, –60 dBFS (rel 1% THD) | 105 | dB | ||
| Pidle | Power dissipation due to idle losses (IPVDD_X) | PO = 0, All channels switching(2) | 0.8 | W | ||
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
6.9 Typical Characteristics
6.9.1 Typical Characteristics, BTL Configuration
Measurement conditions are: 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted.
Figure 1. Total Harmonic + Noise vs Output Power, 1 kHz
Figure 3. Total Harmonic Distortion + Noise vs Frequency, 4 Ω
Figure 5. System Efficiency vs Output Power
Figure 7. Output Power vs Temperature
Figure 2. Output Power vs Supply Voltage vs Distortion + Noise = 10%
Figure 4. Output Power vs Supply Voltage, vs Distortion + Noise = 1%
Figure 6. System Power Loss vs Output Power
Figure 8. Noise Amplitude vs Frequency
6.9.2 Typical Characteristics, SE Configuration
Measurement conditions are: 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, CDCB = 470 µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted.
Figure 9. Total Harmonic Distortion + Noise vs Output Power
Figure 10. Output Power vs Supply Voltage
6.9.3 Typical Characteristics, PBTL Configuration
Measurement conditions are: 1 kHz, PVDD_X = 32.5 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20 Hz to 20 kHz BW (AES17 low pass filter), unless otherwise noted.
Figure 11. Total Harmonic Distortion + Noise vs Output Power
Figure 12. Output Power vs Supply Voltage