7.3.1 System Power-Up and Power-Down Sequence

7.3.2 Start-up and Shutdown Ramp Sequence

The integrated start-up and stop sequence ensures a click and pop free startup and shutdown sequence of the amplifier. The start-up sequence uses a voltage ramp with a duration set by the CSTART capacitor. The sequence uses the input PWM signals to generate output PWM signals, hence input idle PWM should be present during both start-up and shut down ramping sequences.

VDD, GVDD_X and PVDD_X power supplies must be turned on and with settled outputs before starting
the start-up ramp by setting RESET high.

During start-up and shutdown ramp the input PWM signals should be in muted condition with the PWM processor noise shaper activity turned off (50% duty cycle).

The duration of the start-up and shutdown ramp is 100 ms + X ms, where X is the CSTART capacitor value in nF.

It is recommended to use 100nF CSTART in BTL and PBTL mode and 1 µF in SE mode configuration. This results in ramp times of 200 ms and 1.1s respectively. The longer ramp time in SE configuration allows charge and discharge of the output AC coupling capacitor without audible artifacts.

Figure 15. Start-up/Shutdown Ramp

7.3.3 Unused Output Channels

If all available output channels are not used, it is recommended to disable switching of unused output nodes to reduce power consumption. Furthermore by disabling unused output channels the cost of unused output LC demodulation filters can be avoided.

Disabling a channel is done by leave the bootstrap capacitor (BST) unstuffed and connecting the respective input to GND. The unused output pin(s) can be left floating. Please note that the PVDD decoupling capacitors still need to be mounted.

7.3.4 Device Protection System

The TAS5622A contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TAS5622A responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been removed, that is, the supply voltage has increased.

The device will function on errors, as shown in the following table.

Bootstrap UVP does not shutdown according to the table, it shuts down the respective high-side FET.

7.3.5 Pin-to-Pin Short Circuit Protection (PPSC)

The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is shorted to GND or PVDD_X. For comparison, the OC protection system detects an overcurrent after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at start-up, that is, when VDD is supplied, consequently a short to either GND or PVDD_X after system start-up will not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridges are kept in a Hi-Z state until the short is removed, the device then continues the start-up sequence and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that there are no shorts from OUT_X to GND, the second step tests that there are no shorts from OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is <15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the device will not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system it is recommended not to insert resistive load to GND or PVDD_X.

7.3.6 Overtemperature Protection

The TAS5622A has a two-level temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (typical). If the device junction temperature exceeds 155°C (typical) the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.

7.3.7 Overtemperature Warning, OTW

The over temperature warning OTW asserts when the junction temperature has exceeded recommended operating temperature. Operation at junction temperatures above OTW threshold is exceeding recommended operation conditions and is strongly advised to avoid.

If OTW asserts, action should be taken to reduce power dissipation to allow junction temperature to decrease until it gets below the OTW hysteresis threshold. This action can be decreasing audio volume or turning on a system cooling fan.

7.3.8 Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5622A fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold.

7.3.9 Error Reporting

Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI recommends monitoring the OTW signal using the system micro controller and responding to an overtemperature warning signal by, for example, turning down the volume to prevent further heating of the device resulting in device shutdown (OTE).

To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT, CLIP, and OTW outputs. See Electrical Characteristics for actual values.

The FAULT, OTW, pins are active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device.

Any fault resulting in device shutdown is signaled by the FAULT pin going low. Likewise, OTW goes low when the device junction temperature exceeds 125°C (see the following table).

7.3.10 Fault Handling

If a fault situation occurs while in operation, the device will act accordingly to the fault being a global or a channel fault. A global fault is a chip-wide fault situation and will cause all PWM activity of the device to be shut down, and will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET (RESET high) if the OTW signal is cleared (high). A channel fault will result in shutdown of the PWM activity of the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI recommends monitoring the OTW signal using the system micro controller and responding to an over temperature warning signal by, for example, turning down the volume to prevent further heating of the device resulting in device shutdown (OTE).

7.3.11 Device Reset

When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance (Hi-Z) state.

In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the FAULT output, that is, FAULT is forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure thermal reliability, the rising edge of RESET must occur no sooner than 4 ms after the falling edge of FAULT.