ZHCSET5B May   2015  – February 2016 TAS5720L , TAS5720M

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable I2C Address
      2. 7.3.2 I2C Interface
        1. 7.3.2.1 Writing to the I2C Interface
        2. 7.3.2.2 Reading from the I2C Interface
      3. 7.3.3 Serial Audio Interface (SAIF)
        1. 7.3.3.1 Stereo I2S Format Timing
        2. 7.3.3.2 Stereo Left-Justified Format Timing
        3. 7.3.3.3 Stereo Right-Justified Format Timing
        4. 7.3.3.4 TDM Format Timing
      4. 7.3.4 Audio Signal Path
        1. 7.3.4.1 High-Pass Filter (HPF)
        2. 7.3.4.2 Amplifier Analog Gain and Digital Volume Control
        3. 7.3.4.3 Digital Clipper
        4. 7.3.4.4 Class-D Amplifier Settings
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SDZ)
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 Mute Mode
      5. 7.4.5 Faults and Status
    5. 7.5 Register Maps
      1. 7.5.1 Device Identification
      2. 7.5.2 Power Control Register
      3. 7.5.3 Digital Control Register 1
      4. 7.5.4 Digital Control Register 2
      5. 7.5.5 Volume Control Register
      6. 7.5.6 Analog Control Register
      7. 7.5.7 Fault Configuration and Error Status Register
      8. 7.5.8 Digital Clipper 2
      9. 7.5.9 Digital Clipper 1
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Design Procedure
        1. 8.2.2.1 Overview
        2. 8.2.2.2 Select the PWM Frequency
        3. 8.2.2.3 Select the Amplifier Gain and Digital Volume Control
        4. 8.2.2.4 Select Input Capacitance
        5. 8.2.2.5 Select Decoupling Capacitors
        6. 8.2.2.6 Select Bootstrap Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关链接
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

RSM Package
VQFN 32 PINS
Top View
TAS5720L TAS5720M po_slos903.gif

Pin Functions

PIN I/O/P(1) DESCRIPTION
NAME NO.
ADR1 12 I I2C address inputs. Each pin can detect a short to DVDD, a short to GND, a 22-kΩ connection to GND, and a 22-kΩ connection to DVDD.
ADR0 13 I
AVDD 28 P Analog power supply input. Connect directly to PVDD.
BST_N 18 P Class-D Amplifier negative bootstrap. Connect to a capacitor between BST_N and OUT_N.
BST_P 23 P Class-D Amplifier positive bootstrap. Connect to a capacitor between BST_P and OUT_P.
DVDD 11 P Digital power supply. Connect to a 3.3-V supply with external decoupling capacitor.
FAULTZ 2 O Open drain active low fault flag. Pull up on PCB with resistor to DVDD.
LRCLK 4 I TDM interface frame synchronization.
GND 10 P Ground. Connect to PCB ground plane.
29
GVDD 30 O Class-D amplifier gate drive regulator output. Connect decoupling cap to PCB ground plane.
MCLK 5 I Device master clock.
PGND 19 P Power ground. Connect to PCB ground plane.
20
21
22
PVDD 14 P Class-D amplifier power supply input. Connect to PVDD supply and decouple externally.
15
26
27
OUT_N 16 O Class-D amplifier negative output.
17
OUT_P 24 O Class-D amplifier positive output.
25
BCLK 6 I TDM Interface serial bit clock.
SCL 8 I I2C clock Input. Pull up on PCB with a 2.4-kΩ resistor.
SDA 9 I/O I2C bi-directional data. Pull up on PCB with a 2.4-kΩ resistor.
SDIN 7 I TDM interface data input.
SDZ 3 I Active low shutdown signal. Assert low to hold device inactive.
Thermal Pad 33 G Connect to GND for best system performance. If not connected to GND, leave floating.
VCOM 32 O Common mode reference output. Connect decoupling capacitor to the VREF_N pin.
VREF_N 1 P Negative reference for analog. Connect to VCOM and VREG capacitor negative pins.
VREG 31 O Analog regulator output. Connect decoupling capacitor to the VREF_N pin.
(1) I = input, O = output, P = power, I/O = bi-directional
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