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6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage⁽²⁾	PVDD, AVDD (TAS5720L)	–0.3	20	V
	PVDD, AVDD (TAS5720M)	–0.3	30
	DVDD	–0.3	4
Digital input voltage	Digital inputs referenced to DVDD supply	–0.5	V_DVDD + 0.5	V
Ambient operating temperature, T_A		–25	85	°C
Storage temperature, T_stg		–40	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.

(2) All voltages are with respect to network ground pin.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	TYP	MAX	UNIT
PVDD/ AVDD	Power supply voltage	TAS5720L	4.5		16.5	V
PVDD/ AVDD	Power supply voltage	TAS5720M	4.5		26.4	V
DVDD	Power supply voltage		3	3.3	3.6	V
V_IH(DR)	High-level digital input voltage			V_DVDD		V
V_IL(DR)	Low-level digital input voltage			0		V
R_SPK	Minimum speaker load		3.2			Ω
T_A	Operating free-air temperature		–25		85	°C
T_J	Operating junction temperature		–25		150	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TAS5720x	UNIT
		RSM (VQFN)
		32 PINS
R_θJA	Junction-to-ambient thermal resistance	37.3	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	30.4	°C/W
R_θJB	Junction-to-board thermal resistance	7.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	7.7	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance	2.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

T_A = 25ºC, V_(PVDD) = 15 V, V_(DVDD) = 3.3 V, R_L = 4 Ω, f_IN = 1 kHz, f_s = 48 kHz, f_(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1, Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction filter at the device output.

PARAMETER		CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUT AND OUTPUT
V_IH	High-level digital input logic voltage threshold	All digital pins	70% V_DVDD
V_IL	Low-level digital input logic voltage threshold	All digital pins			30% V_DVDD
I_IH	Input logic "high" leakage for digital inputs	All digital pins, excluding SDZ			15	µA
I_IL	Input logic "low" leakage for digital inputs	All digital pins, excluding SDZ			–15	µA
I_IH(SDZ)	Input logic "high" leakage for SDZ inputs	SDZ			1	µA
I_IL(SDZ)	Input logic "low" leakage for SDZ inputs	SDZ			–1	µA
V_OL	Output logic "low" for FAULTZ open drain Output	I_OL= –2 mA			10% V_DVDD
C_IN	Input capacitance for digital inputs	All digital pins		5		pF
MASTER CLOCK
D_(MCLK)	Allowable MCLK duty cycle		45%	50%	55%
f_(MCLK)	MCLK input frequency				25	MHz
	Supported single-speed MCLK frequencies	Values: 64, 128, 256, and 512	64 × f_S		512 × f_S
	Supported double-speed MCLK frequencies	Values: 64, 128, and 256	64 × f_S		256 × f_S
SERIAL AUDIO PORT
D_(BCLK)	Allowable BCLK duty cycle		45%	50%	55%
f_(BCLK)	BCLK input frequency				25	MHz
	Supported single-speed BCLK frequencies	Values: 64, 128, 256, and 512	64 × f_S		512 × f_S
	Supported double-speed BCLK frequencies	Values: 64, 128, and 256	64 × f_S		256 × f_S
f_S	Supported single-speed input sample rates	Values: 44.1 and 48	44.1		48	kHz
f_S	Supported double-speed input sample rates	Values: 88.2 and 96	88.2		96	kHz
I²C CONTROL PORT
C_L(I2C)	Allowable load capacitance for each I²C Line				400	pF
f_SCL	SCL frequency	No wait states			400	kHz
PROTECTION
OTE_(THRESH)	Overtemperature error (OTE) threshold			150		°C
OTE_(HYST)	Overtemperature error (OTE) hysteresis			15		°C
OCE_(THRESH)	Overcurrent error (OCE) threshold	V_(PVDD) = 16.5 V, T_A= 25°C		6		A
DCE_(THRESH)	DC error (DCE) threshold	V_(PVDD) = 16.5 V, TA = 25°C		2.6		V
AMPLIFIER PERFORMANCE
P_OUT	Continuous average power	R_L= 4 Ω, 10% THD+N, V_(PVDD) = 7.2 V, f_IN = 1 kHz		6.6		W
		R_L= 8 Ω, 10% THD+N, V_(PVDD) = 7.2 V, f_IN = 1 kHz		3.7
		R_L= 4 Ω, 10% THD+N, V_(PVDD) = 12 V, f_IN = 1 kHz		17.8
		R_L= 8 Ω, 10% THD+N, V_(PVDD) = 12 V, f_IN = 1 kHz		10.1
		R_L= 4 Ω, 10% THD+N, V_(PVDD) = 15 V, f_IN = 1 kHz, T_A= 60°C		27.4
		R_L= 8 Ω, 10% THD+N, V_(PVDD) = 15 V, f_IN = 1 kHz		15.8
		R_L= 4 Ω, 10% THD+N, V_(PVDD) = 19 V, f_IN = 1 kHz		27
		R_L= 8 Ω, 10% THD+N, V_(PVDD) = 19 V, f_IN = 1 kHz		25.3
		R_L= 4 Ω, 10% THD+N, V_(PVDD) = 24 V, f_IN = 1 kHz		22.1
		R_L= 8 Ω, 10% THD+N, V_(PVDD) = 24 V, f_IN = 1 kHz		39.8
THD+N	Total harmonic distortion plus noise	R_L= 4 Ω,V_(PVDD) = 7.2 V, P_OUT = 1 W, f_IN = 1 kHz		0.033%
		R_L= 8 Ω,V_(PVDD) = 7.2 V, P_OUT = 1 W, f_IN = 1 kHz		0.015%
		R_L= 4 Ω, V_(PVDD)= 12 V, P_OUT = 1 W, f_IN = 1 kHz		0.03%
		R_L= 8 Ω, V_(PVDD)= 12 V, P_OUT = 1 W, 20 Hz ≤ f_IN ≤ 20 kHz		0.013v
		R_L= 4 Ω, V_(PVDD) = 15 V, P_OUT = 1 W, 20 Hz ≤ f_IN≤ 20 kHz		0.028%
		R_L= 8 Ω, V_(PVDD) = 15 V, P_OUT = 1 W, 20 Hz ≤ f_IN≤ 20 kHz		0.012%
		R_L= 4 Ω, V_(PVDD) = 19 V, P_OUT = 1 W, 20 Hz ≤ f_IN ≤ 20 kHz		0.026%
		R_L= 8 Ω, V_(PVDD) = 19 V, P_OUT = 1 W, 20 Hz ≤ f_IN ≤ 20 kHz		0.013%
		R_L= 4 Ω, V_(PVDD) = 24 V, P_OUT = 1 W, 20 Hz ≤ f_IN ≤ 20 kHz		0.026%
		R_L= 8 Ω, V_(PVDD) = 24 V, P_OUT = 1 W, 20 Hz ≤ f_IN ≤ 20 kHz		0.016%
P_EFF	Power efficiency	R_L= 8 Ω, V_(PVDD) = 12 V, P_OUT = 9 W		91%
		R_L= 8 Ω, V_(PVDD) = 12 V, P_OUT = 9 W; f_PWM = 384 kHz		90%
		R_L= 8 Ω, V_(PVDD) = 24 V, P_OUT = 40 W		90%
V_N	Integrated noise floor voltage	A-Weighted,R_L= 8 Ω, Gain = 20.7 dBV		50		µVrms
φ_CC	Channel-to-channel phase shift	Output phase shift between multiple devices from 20 Hz to 20 kHz. Across all sample frequencies and SAIF operating modes.		0.2		deg
A_(RIPPLE)	Frequency response	Maximum deviation above or below passband gain.		±0.15		dB
	-3 dB Output Cutoff Frequency			0.47 × f_S		Hz
AV₍₀₀₎	Amplifier analog gain⁽¹⁾	ANALOG_GAIN[1:0] register bits set to "00"		19.2		dBV
AV₍₀₁₎		ANALOG_GAIN[1:0] register bits set to "01"		20.7
AV₍₁₀₎		ANALOG_GAIN[1:0] register bits set to "10"		23.5
AV₍₁₁₎		ANALOG_GAIN[1:0] register bits set to "11"		26.3
AV_(ERROR)	Amplifier analog gain error				±0.15	dB
V_OS	DC output offset voltage	Measured between OUTP and OUTN		1.5		mV
KCP	Click-pop performance			–60		dBV
PSRR	Power supply rejection ratio	DC, 5.5 V ≤ V_(PVDD) ≤ 26.4 V		87		dB
		AC, V_(PVDD)= 16.5 V + 100 mV_P-P, f_(RIPPLE) from 20 Hz to 10 kHz		53
		AC, V_(PVDD)= 16.5 V + 100 mV_P-P, f_(RIPPLE) from 10 Hz to 20 kHz		50
R_DS(on)FET	Power stage FET on-resistance	T_A = 25°C		120		mΩ
R_DS(on)TOT	Power stage total on-resistance (FET+bond+package)	T_A = 25°C		150		mΩ
I_PK	Peak output current	T_A = 25°C		5		A
f_(HP)	–3 dB high-pass filter corner frequency	f = 44.1 kHz		3.675		Hz
		f = 48 kHz		4
		f = 88.2 kHz		7.35
		f = 96 kHz		8
f_(PWM)	PWM switching frequency	Values: 6, 8, 10, 12, 14, 16, 20, and 24	6		24	f_S

(1) When PVDD is less than 5.5 V, the voltage regulator that operates the analog circuitry does not have enough headroom to maintain the nominal 5.4-V internal voltage. The lack of headroom causes a direct reduction in gain (approximately –0.8 dB at 5 V and –1.74 dB at 4.5 V), but the device functions properly down to V_PVDD = 4.5 V.

6.6 Timing Requirements

			MIN	NOM	MAX	UNIT
t_ACTIVE	Shutdown to Active Time	From deassertion of SDZ (both pin and I²C register bit) until the Class-D amplifier begins switching.		25		ms
t_WAKE	Wake Time	From the deassertion of SLEEP until the Class-D amplifier starts switching.		1
t_SLEEP	Sleep Time	From the assertion of SLEEP until the Class-D amplifier stops switching.		t_vrmp+ 1
t_MUTE	Play to Mute Time	From the assertion of MUTE mode until the volume has ramped to the minimum.		t_vrmp
t_PLAY	Un-Mute to Play Time	From the deassertion of MUTE until the volume has returned to its current setting.		t_vrmp
t_SD	Active to Shutdown Time	From the assertion of SDZ (pin or I²C register bit) until the Class-D amplifier stops switching.		t_vrmp + 1
SERIAL AUDIO PORT
t_{H_L}	Time high and low, BCLK, LRCLK, SDIN inputs		10			ns
t_SU t_HLD	Setup and hold time. LRCLK, SDIN input to BCLK edge.	Input t_RISE ≤ 1 ns, input t_FALL ≤ 1 ns			5	ns
		Input t_RISE ≤ 4 ns, input t_FALL ≤ 4 ns	8
		Input t_RISE ≤ 8 ns, input t_FALL ≤ 8 ns	12
t_RISE	Rise-time BCLK, LRCLK, SDIN inputs				8	ns
t_FALL	Fall-time BCLK, LRCLK, SDIN inputs				8
I²C CONTROL PORT
t_BUS	Bus free time between start and stop conditions		1.3			µs
t_HOLD1(I2C)	Hold Time, SCL to SDA		80			ns
t_HOLD2(I2C)	Hold Time, start condition to SCL		0.6			µs
t_START(I2C)	I2C Startup Time after DVDD Power On Reset				12	ms
t_RISE(I2C)	Rise Time, SCL and SDA				300	ns
t_FALL(I2C)	Fall Time, SCL and SDA				300	ns
t_SU1(I2C)	Setup, SDA to SCL		100			ns
t_SU2(I2C)	Setup, SCL to start condition		0.6			µs
t_SU3(I2C)	Setup, SCL to stop condition		0.6			µs
t_W(H)	Required pulse duration, SCL "HIGH"		0.6			µs
t_W(L)	Required pulse duration, SCL "LOW"		1.3			µs
PROTECTION
t_FAULTZ	Amplifier fault time-out period	DC detect error		650		ms
t_FAULTZ	Amplifier fault time-out period	OTE or OCE fault		1.3		s

When SDZ is deasserted (and the device is not in sleep mode), the amplifier begins to switch after a period of t_ACTIVE. At this point, the volume ramps from –100 dB to the programmed digital volume control (DVC) setting at a rate of 0.5 dB every eight sample periods. Ramping the volume prevents audible artifacts that can occur if discontinuous volume changes are applied while audio is being played back. This period, t_VRMP, depends on the DVC setting and sample rate. Typical values for t_VRMP for a DVC of 0 dB are shown in Timing Requirements. Figure 4 illustrates mode timing.

The time to enter or exit sleep or mute and the time to enter shudown are dominated by t_VRMP. Table 1 lists the timing parameters based on t_VRMP.

TAS5720L TAS5720M mode_timing_slos852.gif

Figure 4. Mode Timing

Table 1. Typical DVC Ramp Times

SAMPLE RATE (kHZ)	RAMP TIMES (t_VRAMP) FROM –100 dB to 0 dB (ms)
44.1	36.3
48	33.3
88.2	18.1
96	16.7

6.7 Typical Characteristics

T_A = 25ºC, V_(PVDD) = 15 V, V_(DVDD) = 3.3 V, R_L = 4 Ω, f_IN = 1 kHz, f_s = 48 kHz, f_(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1, Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction filter at the device output.