ZHCSEX0A March   2016  – March 2016 TAS5733L

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Speaker Amplifier Characteristics
    7. 6.7  Protection Characteristics
    8. 6.8  Master Clock Characteristics
    9. 6.9  I²C Interface Timing Requirements
    10. 6.10 Serial Audio Port Timing Requirements
    11. 6.11 Typical Characteristics - Stereo BTL Mode
    12. 6.12 Typical Characteristics - Mono PBTL Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Audio Signal Processing Overview
    4. 7.4 Feature Description
      1. 7.4.1 Clock, Autodetection, and PLL
      2. 7.4.2 PWM Section
      3. 7.4.3 PWM Level Meter
      4. 7.4.4 Automatic Gain Limiter (AGL)
      5. 7.4.5 Fault Indication
      6. 7.4.6 SSTIMER Pin Functionality
      7. 7.4.7 Device Protection System
        1. 7.4.7.1 Overcurrent (OC) Protection With Current Limiting
        2. 7.4.7.2 Overtemperature Protection
        3. 7.4.7.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
    5. 7.5 Device Functional Modes
      1. 7.5.1 Serial Audio Port Operating Modes
      2. 7.5.2 Communication Port Operating Modes
      3. 7.5.3 Speaker Amplifier Modes
        1. 7.5.3.1 Stereo Mode
        2. 7.5.3.2 Mono Mode
    6. 7.6 Programming
      1. 7.6.1 I²C Serial Control Interface
        1. 7.6.1.1 General I²C Operation
        2. 7.6.1.2 I²C Slave Address
        3. 7.6.1.3 Single- and Multiple-Byte Transfers
        4. 7.6.1.4 Single-Byte Write
        5. 7.6.1.5 Multiple-Byte Write
        6. 7.6.1.6 Single-Byte Read
        7. 7.6.1.7 Multiple-Byte Read
      2. 7.6.2 Serial Interface Control and Timing
        1. 7.6.2.1 Serial Data Interface
        2. 7.6.2.2 I²S Timing
        3. 7.6.2.3 Left-Justified
        4. 7.6.2.4 Right-Justified
      3. 7.6.3 26-Bit 3.23 Number Format
    7. 7.7 Register Maps
      1. 7.7.1 Register Summary
      2. 7.7.2 Detailed Register Descriptions
        1. 7.7.2.1  Clock Control Register (0x00)
        2. 7.7.2.2  Device ID Register (0x01)
        3. 7.7.2.3  Error Status Register (0x02)
        4. 7.7.2.4  System Control Register 1 (0x03)
        5. 7.7.2.5  Serial Data Interface Register (0x04)
        6. 7.7.2.6  System Control Register 2 (0x05)
        7. 7.7.2.7  Soft Mute Register (0x06)
        8. 7.7.2.8  Volume Registers (0x07, 0x08, 0x09)
        9. 7.7.2.9  Volume Configuration Register (0x0E)
        10. 7.7.2.10 Modulation Limit Register (0x10)
        11. 7.7.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
        12. 7.7.2.12 PWM Shutdown Group Register (0x19)
        13. 7.7.2.13 Start/Stop Period Register (0x1A)
        14. 7.7.2.14 Oscillator Trim Register (0x1B)
        15. 7.7.2.15 BKND_ERR Register (0x1C)
        16. 7.7.2.16 Input Multiplexer Register (0x20)
        17. 7.7.2.17 PWM Output MUX Register (0x25)
        18. 7.7.2.18 AGL Control Register (0x46)
        19. 7.7.2.19 PWM Switching Rate Control Register (0x4F)
        20. 7.7.2.20 Bank Switch and EQ Control (0x50)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection Criteria
        1. 8.1.1.1 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
        2. 8.1.1.2 Amplifier Output Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Bridge Tied Load Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Component Selection and Hardware Connections
          2. 8.2.1.2.2 Control and Software Integration
          3. 8.2.1.2.3 I²C Pullup Resistors
          4. 8.2.1.2.4 Digital I/O Connectivity
          5. 8.2.1.2.5 Recommended Startup and Shutdown Procedures
            1. 8.2.1.2.5.1 Start-Up Sequence
            2. 8.2.1.2.5.2 Normal Operation
            3. 8.2.1.2.5.3 Shutdown Sequence
            4. 8.2.1.2.5.4 Power-Down Sequence
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Mono Parallel Bridge Tied Load Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Decoupling Capacitors
      2. 10.1.2 Thermal Performance and Grounding
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 商标
    2. 11.2 静电放电警告
    3. 11.3 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DCA Package
48-Pin HTSSOP With PowerPAD™
Top View
TAS5733L PO_TAS5729xD_48DCA_slase77.gif

Pin Functions

PIN TYPE(2) DESCRIPTION
NAME NO.
ADR/FAULT 19 DI/DO Dual function terminal which sets the LSB of the I²C Address to 0 if pulled to GND, 1 if pulled to AVDD. Also, if configured to be a fault output by the methods described in the Fault Indication section, this terminal will be pulled low when an internal fault occurs.
AGND 35 P Ground reference for analog circuitry (NOTE: This terminal should be connected to the system ground)
AMP_OUT_A 6 AO Speaker amplifier outputs
AMP_OUT_B 2
3
AMP_OUT_C 46
47
AMP_OUT_D 43
AVDD 18 P Power supply for internal analog circuitry
AVDD_REF 17 P Internal power supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)
AVDD_REG 38 P Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)
BSTRP_A 9 P Connection points to for the bootstrap capacitors, which are used to create a power supply for the gate drive for the high-side device
BSTRP_B 1
BSTRP_C 48
BSTRP_D 40
DGND 34 P Ground reference for digital circuitry (NOTE: This terminal should be connected to the system ground)
DVDD 33 P Power supply for the internal digital circuitry
DVDD_REG 23 P Voltage regulator derived from DVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)
GVDD_REG 39 P Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)
LRCLK 25 DI Word select clock for the digital signal that is active on the input data line of the serial port
MCLK 20 DI Master clock used for internal clock tree and sub-circuit/state machine clocking
NC(1) 12 P Not connected inside the device (all "no connect" terminals should be connected to system ground)
13
30
36
37
OSC_GND 22 P Ground reference for oscillator circuitry (NOTE: These terminals should be connected to the system ground)
OSC_RES 21 AO Connection point for precision resistor used by internal oscillator circuit. Details for this resistor are shown in the Typical Applications section
PBTL 11 DI Places the power stage in BTL mode when pulled low, or in PBTL mode when pulled high
PDN 24 DI Places the device in power down when pulled low
PGND 4 — Ground reference for power device circuitry (NOTE: This terminal should be connected to the system ground)
5
44
45
PLL_FLTM 15 AO Negative connection point for the PLL loop filter components
PLL_FLTP 16 AO Positive connection point for the PLL loop filter components
PLL_GND 14 P Ground reference for PLL circuitry (NOTE: This terminal should be connected to the system ground)
PVDD 7 P Power supply for internal power circuitry
8
41
42
RST 31 DI Places the devices in reset when pulled low
SCL 29 DI I²C serial control port clock
SCLK 26 DI Bit clock for the digital signal that is active on the input data line of the serial data port
SDA 28 DI/DO I²C serial control port data
SDIN 27 DI Data line to the serial data port
SSTIMER 10 AO Connection point for the capacitor that is used by the ramp timing circuit, as described in the SSTIMER Pin Functionality section
TEST 32 — Used by TI for testing during device production (NOTE: This terminal should be connected to system ground)
PowerPAD — P Exposed metal pad on the underside of the device, which serves as an electrical connection point for ground as well as a heat conduction path from the device into the board (NOTE: This terminal should be connected to ground through a land pattern defined in the Mechanical Data section)
(1) Although these pins are not connected internally, optimum thermal performance is realized when these pins are connected to the ground plane. Doing so allows copper on the PCB to fill up to and including these pins, providing a path for heat to conduct away from the device and into the surrounding PCB area.
(2) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
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