ZHCSEX0A March   2016  – March 2016 TAS5733L

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Speaker Amplifier Characteristics
    7. 6.7  Protection Characteristics
    8. 6.8  Master Clock Characteristics
    9. 6.9  I²C Interface Timing Requirements
    10. 6.10 Serial Audio Port Timing Requirements
    11. 6.11 Typical Characteristics - Stereo BTL Mode
    12. 6.12 Typical Characteristics - Mono PBTL Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Audio Signal Processing Overview
    4. 7.4 Feature Description
      1. 7.4.1 Clock, Autodetection, and PLL
      2. 7.4.2 PWM Section
      3. 7.4.3 PWM Level Meter
      4. 7.4.4 Automatic Gain Limiter (AGL)
      5. 7.4.5 Fault Indication
      6. 7.4.6 SSTIMER Pin Functionality
      7. 7.4.7 Device Protection System
        1. 7.4.7.1 Overcurrent (OC) Protection With Current Limiting
        2. 7.4.7.2 Overtemperature Protection
        3. 7.4.7.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
    5. 7.5 Device Functional Modes
      1. 7.5.1 Serial Audio Port Operating Modes
      2. 7.5.2 Communication Port Operating Modes
      3. 7.5.3 Speaker Amplifier Modes
        1. 7.5.3.1 Stereo Mode
        2. 7.5.3.2 Mono Mode
    6. 7.6 Programming
      1. 7.6.1 I²C Serial Control Interface
        1. 7.6.1.1 General I²C Operation
        2. 7.6.1.2 I²C Slave Address
        3. 7.6.1.3 Single- and Multiple-Byte Transfers
        4. 7.6.1.4 Single-Byte Write
        5. 7.6.1.5 Multiple-Byte Write
        6. 7.6.1.6 Single-Byte Read
        7. 7.6.1.7 Multiple-Byte Read
      2. 7.6.2 Serial Interface Control and Timing
        1. 7.6.2.1 Serial Data Interface
        2. 7.6.2.2 I²S Timing
        3. 7.6.2.3 Left-Justified
        4. 7.6.2.4 Right-Justified
      3. 7.6.3 26-Bit 3.23 Number Format
    7. 7.7 Register Maps
      1. 7.7.1 Register Summary
      2. 7.7.2 Detailed Register Descriptions
        1. 7.7.2.1  Clock Control Register (0x00)
        2. 7.7.2.2  Device ID Register (0x01)
        3. 7.7.2.3  Error Status Register (0x02)
        4. 7.7.2.4  System Control Register 1 (0x03)
        5. 7.7.2.5  Serial Data Interface Register (0x04)
        6. 7.7.2.6  System Control Register 2 (0x05)
        7. 7.7.2.7  Soft Mute Register (0x06)
        8. 7.7.2.8  Volume Registers (0x07, 0x08, 0x09)
        9. 7.7.2.9  Volume Configuration Register (0x0E)
        10. 7.7.2.10 Modulation Limit Register (0x10)
        11. 7.7.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
        12. 7.7.2.12 PWM Shutdown Group Register (0x19)
        13. 7.7.2.13 Start/Stop Period Register (0x1A)
        14. 7.7.2.14 Oscillator Trim Register (0x1B)
        15. 7.7.2.15 BKND_ERR Register (0x1C)
        16. 7.7.2.16 Input Multiplexer Register (0x20)
        17. 7.7.2.17 PWM Output MUX Register (0x25)
        18. 7.7.2.18 AGL Control Register (0x46)
        19. 7.7.2.19 PWM Switching Rate Control Register (0x4F)
        20. 7.7.2.20 Bank Switch and EQ Control (0x50)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection Criteria
        1. 8.1.1.1 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
        2. 8.1.1.2 Amplifier Output Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Bridge Tied Load Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Component Selection and Hardware Connections
          2. 8.2.1.2.2 Control and Software Integration
          3. 8.2.1.2.3 I²C Pullup Resistors
          4. 8.2.1.2.4 Digital I/O Connectivity
          5. 8.2.1.2.5 Recommended Startup and Shutdown Procedures
            1. 8.2.1.2.5.1 Start-Up Sequence
            2. 8.2.1.2.5.2 Normal Operation
            3. 8.2.1.2.5.3 Shutdown Sequence
            4. 8.2.1.2.5.4 Power-Down Sequence
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Mono Parallel Bridge Tied Load Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Decoupling Capacitors
      2. 10.1.2 Thermal Performance and Grounding
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 商标
    2. 11.2 静电放电警告
    3. 11.3 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
Supply voltage DVDD, AVDD –0.3 to 3.6 V
PVDD –0.3 to 20
Input voltage 3.3-V digital input –0.5 to DVDD + 0.5 V
5-V tolerant(2) digital input (except MCLK) –0.5 to DVDD + 2.5(4)
5-V tolerant MCLK input –0.5 to AVDD + 2.5(4)
AMP_OUT_x to GND 22(3) V
BSTRP_x to GND 29(3) V
Operating free-air temperature 0 to 85 °C
Storage temperature range, Tstg –40 to 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RST, SCLK, LRCK, MCLK, SDIN, SDA, and SCL.
(3) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
(4) Maximum pin voltage should not exceed 6 V.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
DVDD, AVDD Digital, analog supply voltage 3 3.3 3.6 V
PVDD Output power devices supply voltage 8 16.5(1)(2) V
VIH High-level input voltage 5-V tolerant 2 V
VIL Low-level input voltage 5-V tolerant 0.8 V
TA Operating ambient temperature range 0 85 °C
TJ (2) Operating junction temperature range 0 125 °C
RL Load impedance 4 8 Ω
RL Load impedance in PBTL 2 Ω
LO Output-filter inductance Minimum output inductance under short-circuit condition 10 μH
(1) For operation at PVDD levels greater than 14.5 V, the modulation limit must be set to 96.1% or lower via the control port register 0x10.
(2) 16.5 V is the maximum recommended voltage for continuous operation of the TAS5733L device. Testing and characterization of the device is performed up to and including 16.5 V to ensure “in system” design margin. However, continuous operation at these levels is not recommended. Operation above the maximum recommended voltage may result in reduced performance, errant operation, and reduction in device reliability.

6.4 Thermal Characteristics

THERMAL METRIC(1) DCA (48 PINS) UNITS
Special Test Case JEDEC Standard 2-Layer PCB JEDEC Standard 4-Layer PCB TAS5733LEVM
θJA Junction-to-ambient thermal resistance(2) 50.7 27.6 25.0 °C/W
θJCtop Junction-to-case (top) thermal resistance(3) 14.9 16.7 °C/W
θJB Junction-to-board thermal resistance(4) 6.9 7.9 °C/W
ψJT Junction-to-top characterization parameter(5) 1.2 0.8 0.7 °C/W
ψJB Junction-to-board characterization parameter(6) 11.8 7.8 5.8 °C/W
θJCbot Junction-to-case (bottom) thermal resistance(7) 1.7 2.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer

6.5 Electrical Characteristics

TA = 25°, PVDD_x = 12 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL BD mode, fS = 48 kHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage ADR/FAULT and SDA IOH = –4 mA
DVDD = AVDD = 3 V		 2.4 V
VOL Low-level output voltage IOL = 4 mA
DVDD = AVDD = 3 V		 0.5 V
IIL Low-level input current Digital Inputs VI < VIL
DVDD = AVDD = 3.6 V 		75 μA
IIH High-level input current VI > VIH
DVDD = AVDD = 3.6 V 		75 μA
IDD 3.3-V supply current 3.3-V supply voltage
(DVDD, AVDD) 		Normal mode 49 68 mA
Reset (RST = low, PDN = high) 23 38

6.6 Speaker Amplifier Characteristics

PVDD = 12 V, BTL BD mode, AVDD = DVDD = 3.3 V, fS = 48 KHz, RL = 8 Ω, audio frequency = 1 kHz, AES17 filter, fPWM = 384 kHz, TA = 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions and as tested on the TAS5733L EVM.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Power output per channel PVDD = 12 V, 10% THD, 1-kHz input signal 10 W
PVDD = 12 V, 7% THD, 1-kHz input signal 9
PVDD = 12 V, 1% THD, 1-kHz input signal 7.5
PVDD = 13.2 V, 10% THD, 1-kHz input signal 12
PVDD = 13.2 V, 7% THD, 1-kHz input signal 11
PVDD = 13.2 V, 1% THD, 1-kHz input signal 9
THD+N Total harmonic distortion + noise PVDD = 12 V, PO = 1 W 0.25 %
PVDD = 13.2 V, PO = 1 W 0.3
Vn Output integrated noise (rms) A-weighted 30 μV
Crosstalk PO = 1 W, f = 1 kHz (BD Mode), PVDD = 12 V –79 dB
PO =1 W, f = 1 kHz (AD Mode), PVDD = 12 V –62 dB
Output switching frequency 11.025, 22.05, 44.1-kHz data rate ±2% 288 kHz
48, 24, 12, 8, 16, 32-kHz data rate ±2% 384
IPVDD Supply current No load (PVDD) Normal mode 16 25 mA
Reset (RST = low, PDN = high) 3 8
rDS(on)(1) Drain-to-source resistance, low side TJ = 25°C, includes metallization resistance 120 mΩ
Drain-to-source resistance, high side TJ = 25°C, includes metallization resistance 120
RPD Internal pulldown resistor at the output of each half-bridge Connected when drivers are in the high-impedance state to provide bootstrap capacitor charge. 3 kΩ
(1) This does not include bond-wire or pin resistance.

6.7 Protection Characteristics

TA = 25°, PVDD_x = 12 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL BD mode, fS = 48 kHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vuvp(fall) Undervoltage protection limit PVDD falling 5.4 V
Vuvp(rise) Undervoltage protection limit PVDD rising 5.8 V
OTE Overtemperature error 150 °C
IOC Overcurrent limit protection 4 A
IOCT Overcurrent response time 150 ns

6.8 Master Clock Characteristics(1)

PVDD = 12 V, BTL BD mode, AVDD = DVDD = 3.3 V, fS = 48 kHz, RL = 8 Ω, audio frequency = 1 kHz, AES17 filter, fPWM = 384 kHz, TA = 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions (unless otherwise specified).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLL INPUT PARAMETERS
fMCLKI MCLK frequency 2.8224 24.576 MHz
MCLK duty cycle 40% 50% 60%
tr / tf(MCLK) Rise/fall time for MCLK 5 ns
(1) For clocks related to the serial audio port, please see Serial Audio Port Timing Requirements.

6.9 I²C Interface Timing Requirements

MIN NOM MAX UNIT
tw(RST) Pulse duration, RST active 100 μs
td(I²C_ready) Time to enable I²C after RST goes high 13.5 ms
fSCL Frequency, SCL 400 kHz
tw(H) Pulse duration, SCL high 0.6 μs
tw(L) Pulse duration, SCL low 1.3 μs
tr Rise time, SCL and SDA 300 ns
tf Fall time, SCL and SDA 300 ns
tsu1 Setup time, SDA to SCL 100 ns
th1 Hold time, SCL to SDA 0 ns
t(buf) Bus free time between stop and start conditions 1.3 μs
tsu2 Setup time, SCL to start condition 0.6 μs
th2 Hold time, start condition to SCL 0.6 μs
tsu3 Setup time, SCL to stop condition 0.6 μs
CL Load capacitance for each bus line 400 pF

6.10 Serial Audio Port Timing Requirements

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fS CL ≤ 30 pF 1.024 12.288 MHz
tsu1 Setup time, LRCK to SCLK rising edge 10 ns
th1 Hold time, LRCK from SCLK rising edge 10 ns
tsu2 Setup time, SDIN to SCLK rising edge 10 ns
th2 Hold time, SDIN from SCLK rising edge 10 ns
LRCK frequency 8 48 48 kHz
SCLK duty cycle 40% 50% 60%
LRCK duty cycle 40% 50% 60%
SCLK rising edges between LRCK rising edges 32 64 SCLK edges
t(edge) LRCK clock edge with respect to the falling edge of SCLK –1/4 1/4 SCLK period
tr/tf Rise/fall time for SCLK/LRCK 8 ns
LRCK allowable drift before LRCK reset 4 MCLKs
TAS5733L sys_init_tas5733.gif

NOTE:

On power up, hold the TAS5733L RST LOW for at least 100 μs after DVDD has reached 3 V.

NOTE:

If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is deasserted (HIGH).
Figure 1. Reset Timing
TAS5733L t0027-01.gif Figure 2. SCL and SDA Timing
TAS5733L t0028-01.gif Figure 3. Start and Stop Conditions Timing
TAS5733L t0026-04_los556.gif Figure 4. Serial Audio Port Timing

6.11 Typical Characteristics - Stereo BTL Mode

TAS5733L D007_SLASE77_TAS5733L.gif
Figure 5. Output Power vs Supply Voltage - BTL
TAS5733L D001_SLASE77.gif
PVDD = 12 V RL = 8 Ω
Figure 7. THD+N vs Frequency - BTL
TAS5733L D003_SLASE77_TAS5733L.gif
PVDD = 12 V RL = 4 Ω
Figure 9. THD+N vs Frequency - BTL
TAS5733L D005_SLASE77.gif
PVDD = 12 V RL = 6 Ω
Figure 11. THD+N vs Output Power - BTL
TAS5733L D008_SLASE77_TAS5733L.gif
RL = 8 Ω
Total Output Power includes power delivered from both amplifier outputs. For instance, 40 W of total output power means 2 × 20 W, with 20 W delivered by one channel and 20 W delivered by the other channel.
Figure 13. Efficiency vs Total Output Power - BTL
TAS5733L D010_SLASE77.gif
PVDD = 12 V RL = 8 Ω
Figure 15. Crosstalk vs Frequency - BTL
TAS5733L D012_SLASE77_TAS5733L.gif
Figure 6. Idle Channel Noise vs Supply Voltage - BTL
TAS5733L D002_SLASE77.gif
PVDD = 12 V RL = 6 Ω
Figure 8. THD+N vs Frequency - BTL
TAS5733L D004_SLASE77.gif
PVDD = 12 V RL = 8 Ω
Figure 10. THD+N vs Output Power - BTL
TAS5733L D006_SLASE77.gif
PVDD = 12 V RL = 4 Ω
Figure 12. THD+N vs Output Power - BTL
TAS5733L D009_SLASE77_TAS5733L.gif
RL = 4 Ω
Total Output Power includes power delivered from both amplifier outputs. For instance, 40 W of total output power means 2 × 20 W, with 20 W delivered by one channel and 20 W delivered by the other channel.
Figure 14. Efficiency vs Total Output Power - BTL
TAS5733L D011_SLASE77.gif
PVDD = 12 V RL = 4 Ω
Figure 16. Crosstalk vs Frequency - BTL

6.12 Typical Characteristics - Mono PBTL Mode

TAS5733L D013_SLASE77_TAS5733L.gif
PVDD = 12 V RL = 4 Ω
Figure 17. THD+N vs Frequency - PBTL
TAS5733L D015_SLASE77_TAS5733L.gif
PVDD = 12 V RL = 2 Ω
Figure 19. THD+N vs Frequency - PBTL
TAS5733L D017_SLASE77_TAS5733L.gif
PVDD = 12 V RL = 3 Ω
Figure 21. THD+N vs Output Power - PBTL
TAS5733L D019_SLASE77_TAS5733L.gif
Figure 23. Output Power vs PVDD - PBTL
TAS5733L D021_SLASE77_TAS5733L.gif
RL = 2 Ω
Total Output Power includes power delivered from both amplifier outputs. For instance, 40 W of total output power means 2 × 20 W, with 20 W delivered by one channel and 20 W delivered by the other channel.
Figure 25. Efficiency vs Output Power - PBTL
TAS5733L D014_SLASE77_TAS5733L.gif
PVDD = 12 V RL = 3 Ω
Figure 18. THD+N vs Frequency - PBTL
TAS5733L D016_SLASE77_TAS5733L.gif
PVDD = 12 V RL = 4 Ω
Figure 20. THD+N vs Output Power - PBTL
TAS5733L D018_SLASE77_TAS5733L.gif
PVDD = 12 V RL = 2 Ω
Figure 22. THD+N vs Output Power - PBTL
TAS5733L D020_SLASE77_TAS5733L.gif
RL = 4 Ω
Total Output Power includes power delivered from both amplifier outputs. For instance, 40 W of total output power means 2 × 20 W, with 20 W delivered by one channel and 20 W delivered by the other channel.
Figure 24. Efficiency vs Output Power - PBTL
TAS5733L D022_SLASE77_TAS5733L.gif
Figure 26. Idle Channel Noise vs PVDD - PBTL
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