7.6.2.2 I²S Timing

I²S timing uses LRCK to define when the data being transmitted is for the left channel and when the data is for the right channel. LRCK is low for the left channel and high for the right channel. A bit clock running at 32 × f_S, 48 × f_S, or 64 × f_S is used to clock in the data. A delay of one bit clock exists from the time the LRCK signal changes state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused trailing data bit positions.

NOTE:

All data presented in two's-complement form with MSB first.

Figure 55. I²S 64-f_S Format

NOTE:

All data presented in two's-complement form with MSB first.

Figure 56. I²S 48-f_S Format

NOTE:

All data presented in two's-complement form with MSB first.

Figure 57. I²S 32-f_S Format