8.3.3.1 Clock Master Mode from Audio Rate Master Clock

In Master Mode, the device generates bit clock and left-right and frame sync clock and outputs them on the appropriate pins. To configure the device in this mode, first put the device into reset, then use registers SLCKO and LRKO (P0-R9). Then reset the LRCK/FS and SCLK divider counters using bits RSLCK and RLRK (P0-R12). Finally, exit reset.

Figure 62 shows a simplified serial port clock tree for the device in master mode.

Figure 62. Simplified Clock Tree for MLCK Sourced Master Mode

In master mode, MLCK is an input and SCLK and LRCK/FS are outputs. SCLK and LRCK/FS are integer divisions of MLCK. Master mode with a non-audio rate master clock source requires external GPIO’s to use the PLL in standalone mode. The PLL needs to be configured to ensure that the on-chip processor can be driven at its maximum clock rate. This mode of operation is described in theClock Master from a Non-Audio Rate Master Clock section.

When used with audio rate master clocks, the register changes that need to be done include switching the device into master mode, and setting the divider ratio. An example of this mode of operations is using 24.576 MCLK as a master clock source and driving the SCLK and LRCK/FS with integer dividers to create 48 kHz. In this mode, the DAC section of the device is also running from the PLL output. The TAS5756M device is able to meet the specified audio performance while using the internal PLL. However, using the MCLK CMOS oscillator source will have less jitter than the PLL.

To switch the DAC clocks (SDAC in the Figure 61) the following registers should be modified

• Clock Tree Flex Mode (P253-R63 and P253-R64)
• DAC and OSR Source Clock Register (P0-R14). Set to 0x30 (MLCK input, and OSR is set to whatever the DAC source is)
• The DAC clock divider should be 16f_S.
  • 16 × 48 kHz = 768 kHz
  • 24.576 MHz (MLCK in) / 768 kHz = 32
  • Therefore, the divide ratio for register DDAC (P0-R28) should be set to 32. The register mapping gives 0x00 = 1, so 32 must be converter to 0x1F (31dec).

8.3.3.2 Clock Master from a Non-Audio Rate Master Clock

The classic example here is running 12-MHz Master clock for a 48-kHz sampling system. Given the clock tree for the device (shown in Figure 61), a non-audio clock rate cannot be brought into the MLCK to the PLL in master mode. Therefore, the PLL source must be configured to be a GPIO pin, and the output brought back into another GPIO pin.

Figure 63. Generating Audio Clocks Using Non-Audio Clock Sources

The clock flow through the system is shown in Figure 63. The newly generated MLCK must be brought out of the device on a GPIO pin, then brought into the MLCK pin for integer division to create SCLK and LRCK/FS outputs.

8.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)

The TAS5756M device requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the MLCK input and supports up to 50 MHz. The TAS5756M device system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in the bands of 8 kHz, 16 kHz, (32 kHz – 44.1 kHz – 48kHz), (88.2 kHz – 96 kHz), and (176.4 kHz – 192 kHz) are supported.

In the presence of a valid bit MCLK, SCLK and LRCK/FS, the device automatically configures the clock tree and PLL to drive the miniDSP as required.

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 2 shows examples of system clock frequencies for common audio sampling rates.

MLCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are supported by configuring various PLL and clock-divider registers directly. In this mode, auto clock mode should be disabled using P0-R37. Additionally, it may be necessary to ignore clock error detection if external clocks are not-available for some time during configuration or if the clocks presented on the pins of the device or are invalid. This extended programmability allows the device to operate in an advanced mode in which it becomes a clock master and drive the host serial port with LRCK/FS and SLCK, from a non-audio related clock (for example, using a setting of 12 MHz to generate 44.1 kHz [LRCK/FS] and 2.8224 MHz [SLCK]).

Table 2 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low phase jitter and noise. For MCLK timing requirements, refer to the Serial Audio Port Timing – Master Mode section.

8.3.3.4 Clock Slave Mode with SLCK PLL to Generate Internal Clocks (3-Wire PCM)

8.3.3.4.2 PLL Calculation

The TAS5756M device has an on-chip PLL with fractional multiplication to generate the clock frequency needed by the Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 1 MHz to 50 MHz and is register programmable to enable generation of required sampling rates with fine precision.

The PLL is enabled by default. The PLL can be enabled by writing to P0-R4, B[0]. When the PLL is enabled, the PLL output clock PLLCK is given by Equation 1:

Equation 1.

where

• R = 1, 2, 3,4, ... , 15, 16
• J = 4,5,6, . . . 63, and D = 0000, 0001, 0002, . . . 9999
• K = [J value].[D value]
• P = 1, 2, 3, ... 15

R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

8.3.3.4.2.1 Examples:

• If K = 8.5, then J = 8, D = 5000
• If K = 7.12, then J = 7, D = 1200
• If K = 14.03, then J = 14, D = 0300
• If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied:

• 1 MHz ≤ ( PLLCKIN / P ) ≤ 20 MHz
• 64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
• 1 ≤ J ≤ 63

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:

• 6.667 MHz ≤ PLLCLKIN / P ≤ 20 MHz
• 64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
• 4 ≤ J ≤ 11
• R = 1

When the PLL is enabled,

• f_S = (PLLCLKIN × K × R) / (2048 × P)
• The value of N is selected so that f_S × N = PLLCLKIN x K x R / P is in the allowable range.

Example: MCLK = 12 MHz and f_S = 44.1 kHz, (N=2048)

Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example: MCLK = 12 MHz and f_S = 48.0 kHz, (N=2048)

Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Values are written to the registers in Table 4.

Table 4. PLL Registers

DIVIDER	FUNCTION	BITS
PLLE	PLL enable	P0-R4, B[0]
PPDV	PLL P	P0-R20, B[3:0]
PJDV	PLL J	P0-R21, B[5:0]
PDDV	PLL D	P0-R22, B[5:0]
		P0-R23, B[7:0]
PRDV	PLL R	P0-R24, B[3:0]

Table 5. PLL Configuration Recommendations

EQUATIONS	DESCRIPTION
fS (kHz)	Sampling frequency
RMLCK	Ratio between sampling frequency and MLCK frequency (MLCK frequency = RMLCK x sampling frequency)
MLCK (MHz)	System master clock frequency at MLCK input (pin 20)
PLL VCO (MHz)	PLL VCO frequency as PLLCK in Figure 61
P	One of the PLL coefficients in Equation 1
PLL REF (MHz)	Internal reference clock frequency which is produced by MLCK / P
M = K × R	The final PLL multiplication factor computed from K and R as described in Equation 1
K = J.D	One of the PLL coefficients in Equation 1
R	One of the PLL coefficients in Equation 1
PLL fS	Ratio between fS and PLL VCO frequency (PLL VCO / fS)
DSP fS	Ratio between operating clock rate and fS (PLL fS / NMAC)
NMAC	The clock divider value in Table 3
DSP CLK (MHz)	The operating frequency as DSPCK in Figure 61
MOD fS	Ratio between DAC operating clock frequency and fS (PLL fS / NDAC)
MOD f (kHz)	DAC operating frequency as DACCK in
NDAC	DAC clock divider value in Table 3
DOSR	OSR clock divider value in Table 3 for generating OSRCK in Figure 61. DOSR must be chosen so that MOD fS / DOSR = 16 for correct operation.
NCP	NCP (negative charge pump) clock divider value in Table 3
CP f	Negative charge pump clock frequency (fS × MOD fS / NCP)
% Error	Percentage of error between PLL VCO / PLL fS and fS (mismatch error). This value is typically zero but can be non-zero especially when K is not an integer (D is not zero). This value may be non-zero only when the TAS5756M device acts as a master.

The previous equations explain how to calculate all necessary coefficients and controls to configure the PLL. Table 6 provides for easy reference to the recommended clock divider settings for the PLL as a Master Clock.

Table 6. Recommended Clock Divider Settings for PLL as Master Clock

fS (kHz)	RMLCK	MCLK (MHz)	PLL VCO (MHz)	P	PLL REF (MHz)	M = K×R	K = J×D	R	PLL fS	DSP fS	NMAC	DSP CLK (MHz)	MOD fS	MOD f (kHz)	NDAC	DOSR	% ERROR	NCP	CP f (kHz)
8	128	1.024	98.304	1	1.024	96	48	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	192	1.536	98.304	1	1.536	64	32	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	256	2.048	98.304	1	2.048	48	48	1	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	384	3.072	98.304	3	1.024	96	48	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	512	4.096	98.304	3	1.365	72	36	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	768	6.144	98.304	3	2.048	48	48	1	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	1024	8.192	98.304	3	2.731	36	36	1	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	1152	9.216	98.304	9	1.024	96	48	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	1536	12.288	98.304	9	1.365	72	36	2	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	2048	16.384	98.304	9	1.82	54	54	1	12288	1024	12	8.192	768	6144	16	48	0	4	1536
	3072	24.576	98.304	9	2.731	36	36	1	12288	1024	12	8.192	768	6144	16	48	0	4	1536
11.025	128	1.4112	90.3168	1	1.411	64	32	2	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	192	2.1168	90.3168	3	0.706	128	32	4	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	256	2.8224	90.3168	1	2.822	32	32	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	384	4.2336	90.3168	3	1.411	64	32	2	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	512	5.6448	90.3168	3	1.882	48	48	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	768	8.4672	90.3168	3	2.822	32	32	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	1024	11.2896	90.3168	3	3.763	24	24	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	1152	12.7008	90.3168	9	1.411	64	32	2	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	1536	16.9344	90.3168	9	1.882	48	48	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	2048	22.5792	90.3168	9	2.509	36	36	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
	3072	33.8688	90.3168	9	3.763	24	24	1	8192	1024	8	11.2896	512	5644.8	16	32	0	4	1411.2
16	64	1.024	98.304	1	1.024	96	48	2	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	128	2.048	98.304	1	2.048	48	48	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	192	3.072	98.304	1	3.072	32	32	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	256	4.096	98.304	1	4.096	24	24	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	384	6.144	98.304	3	2.048	48	48	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	512	8.192	98.304	3	2.731	36	36	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	768	12.288	98.304	3	4.096	24	24	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	1024	16.384	98.304	3	5.461	18	18	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	1152	18.432	98.304	3	6.144	16	16	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	1536	24.576	98.304	9	2.731	36	36	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	2048	32.768	98.304	9	3.641	27	27	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
	3072	49.152	98.304	9	5.461	18	18	1	6144	1024	6	16.384	384	6144	16	24	0	4	1536
22.05	64	1.4112	90.3168	1	1.411	64	32	2	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	128	2.8224	90.3168	1	2.822	32	32	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	192	4.2336	90.3168	3	1.411	64	32	2	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	256	5.6448	90.3168	1	5.645	16	16	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	384	8.4672	90.3168	3	2.822	32	32	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	512	11.2896	90.3168	3	3.763	24	24	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	768	16.9344	90.3168	3	5.645	16	16	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	1024	22.5792	90.3168	3	7.526	12	12	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	1152	25.4016	90.3168	9	2.822	32	32	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	1536	33.8688	90.3168	9	3.763	24	24	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
	2048	45.1584	90.3168	9	5.018	18	18	1	4096	1024	4	22.5792	256	5644.8	16	16	0	4	1411.2
32	32	1.024	98.304	1	1.024	96	48	2	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	48	1.536	98.304	1	1.536	64	16	4	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	64	2.048	98.304	1	2.048	48	24	2	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	128	4.096	98.304	1	4.096	24	24	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	192	6.144	98.304	3	2.048	48	48	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	256	8.192	98.304	2	4.096	24	24	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	384	12.288	98.304	3	4.096	24	24	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	512	16.384	98.304	3	5.461	18	18	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	768	24.576	98.304	3	8.192	12	12	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	1024	32.768	98.304	3	10.923	9	9	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	1152	36.864	98.304	9	4.096	24	24	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
	1536	49.152	98.304	6	8.192	12	12	1	3072	1024	3	32.768	192	6144	16	12	0	4	1536
44.1	32	1.4112	90.3168	1	1.411	64	32	2	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	64	2.8224	90.3168	1	2.822	32	16	2	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	128	5.6448	90.3168	1	5.645	16	16	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	192	8.4672	90.3168	3	2.822	32	32	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	256	11.2896	90.3168	2	5.645	16	16	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	384	16.9344	90.3168	3	5.645	16	16	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	512	22.5792	90.3168	3	7.526	12	12	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	768	33.8688	90.3168	3	11.29	8	8	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
	1024	45.1584	90.3168	3	15.053	6	6	1	2048	1024	2	45.1584	128	5644.8	16	8	0	4	1411.2
48	32	1.536	98.304	1	1.536	64	32	2	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	64	3.072	98.304	1	3.072	32	16	2	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	128	6.144	98.304	1	6.144	16	16	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	192	9.216	98.304	3	3.072	32	32	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	256	12.288	98.304	2	6.144	16	16	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	384	18.432	98.304	3	6.144	16	16	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	512	24.576	98.304	3	8.192	12	12	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	768	36.864	98.304	3	12.288	8	8	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
	1024	49.152	98.304	3	16.384	6	6	1	2048	1024	2	49.152	128	6144	16	8	0	4	1536
96	32	3.072	98.304	1	3.072	32	16	2	1024	512	2	49.152	64	6144	16	4	0	4	1536
	48	4.608	98.304	3	1.536	64	32	2	1024	512	2	49.152	64	6144	16	4	0	4	1536
	64	6.144	98.304	1	6.144	16	8	2	1024	512	2	49.152	64	6144	16	4	0	4	1536
	128	12.288	98.304	2	6.144	16	16	1	1024	512	2	49.152	64	6144	16	4	0	4	1536
	192	18.432	98.304	3	6.144	16	16	1	1024	512	2	49.152	64	6144	16	4	0	4	1536
	256	24.576	98.304	4	6.144	16	16	1	1024	512	2	49.152	64	6144	16	4	0	4	1536
	384	36.864	98.304	6	6.144	16	16	1	1024	512	2	49.152	64	6144	16	4	0	4	1536
	512	49.152	98.304	8	6.144	16	16	1	1024	512	2	49.152	64	6144	16	4	0	4	1536
192	32	6.144	98.304	1	6.144	16	8	2	512	256	2	49.152	32	6144	16	2	0	4	1536
	48	9.216	98.304	3	3.072	32	16	2	512	256	2	49.152	32	6144	16	2	0	4	1536
	64	12.288	98.304	1	12.288	8	4	2	512	256	2	49.152	32	6144	16	2	0	4	1536
	128	24.576	98.304	2	12.288	8	8	1	512	256	2	49.152	32	6144	16	2	0	4	1536
	192	36.864	98.304	3	12.288	8	8	1	512	256	2	49.152	32	6144	16	2	0	4	1536
	256	49.152	98.304	4	12.288	8	8	1	512	256	2	49.152	32	6144	16	2	0	4	1536

8.3.3.5 Serial Audio Port – Data Formats and Bit Depths

The serial audio interface port is a 3-wire serial port with the signals LRCK/FS (pin 25), SCLK (pin 23), and SDIN (pin 24). SCLK is the serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio interface. Serial data is clocked into the TAS5756M device on the rising edge of SCLK.The LRCK/FS pin is the serial audio left/right word clock or frame sync when the device is operated in TDM Mode.

The TAS5756M device requires the synchronization of LRCK/FS and system clock, but does not need a specific phase relation between LRCK/FS and system clock.

If the relationship between LRCK/FS and system clock changes more than ±5 MCLK, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until re-synchronization between LRCK/FS and system clock is completed.

If the relationship between LRCK/FS and SCLK are invalid more than 4 LRCK/FS periods, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until re-synchronization between LRCK/FS and SCLK is completed.

8.3.3.5.1 Data Formats and Master/Slave Modes of Operation

The TAS5756M device supports industry-standard audio data formats, including standard I²S and left-justified. Data formats are selected via Register (P0-R40). All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. The data formats are detailed in Figure 64 through Figure 69.

The TAS5756M device also supports right-justified and TDM/DSP data. I²S, LJ, RJ, and TDM/DSP are selected using Register (P0-R40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are accepted. Default setting is I²S and 24 bit word length. The I²S slave timing is shown in .

shows a detailed timing diagram for the serial audio interface.

In addition to acting as a I²S slave, the TAS5756M device can act as an I²S master, by generating SCLK and LRCK/FS as outputs from the MCLK input. Table 8 lists the registers used to place the device into Master or Slave mode. Please refer to theSerial Audio Port Timing – Master Mode section for serial audio Interface timing requirements in Master Mode. For Slave Mode timing, please refer to to the Serial Audio Port Timing – Slave Mode section.

Table 8. I²S Master Mode Registers

REGISTER	FUNCTION
P0-R9-B0, B4, and B5	I2S Master mode select
P0-R32-B[6:0]	SCLK divider and LRCK/FS divider
P0-R33-B[7:0]

Figure 64. Left Justified Audio Data Format

I²S Data Format; L-channel = LOW, R-channel = HIGH

Figure 65. I²S Audio Data Format

Right Justified Data Format; L-channel = HIGH, R-channel = LOW

Figure 66. Right Justified Audio Data Format

TDM/DSP Data Format with OFFSET = 0

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 67. TDM/DSP 1 Audio Data Format

TDM/DSP Data Format with OFFSET = 1

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 68. TDM/DSP 2 Audio Data Format

TDM/DSP Data Format with OFFSET = N

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 69. TDM/DSP 3 Audio Data Format

8.3.3.6 Input Signal Sensing (Power-Save Mode)

The TAS5756M device has a zero-detect function. This function can be applied to both channels of data as an AND function or an OR function, via controls provided in the control port in P0-R65-B[2:1].Continuous Zero data cycles are counted by LRCK/FS, and the threshold of decision for analog mute can be set by P0-R59, B[6:4] for the data which is clocked in on the left frame of an I²S signal or Slot 1 of a TDM signal and P0-R59, B[2:0] for the data which is clocked in on the right frame of an I²S signal or Slot 2 of a TDM signal as shown in Table 10. Default values are 0 for both channels.

8.3.3.7 Serial Data Output

If it is supported by the HybridFlow in use, the TAS5756M device can present serial data on one of the three available hardware pins, GPIO0, GPIO1, or GPIO2. In a HybridFlow which supports serial data out, the serial data out origin can always be configured to come before the mini-DSP, by clearing the SDSL bit in P0-R7. This feature is used as a loop-back to check the integrity of the data transmission from the source to the TAS5756M device . In addition to the default loop-back mode, HybridFlows allows the SDOUT signal to originate from either a point after the processing or from some intermediary point within the HybridFlow. This option is accomplished by setting the SDSL bit in P0-R7. Figure 70 shows how to configure the origin of the serial data output signal.

Figure 70. Serial Data Output Signal

Choosing the origin to be after all processing has been applied to the signal (i.e. before it is sent to the amplifier) is popular for sending a monitor signal back to a voice processing or echo-cancelling device elsewhere in the system. Other origins may configure the signal to originate after a subwoofer generation block, which sums in the inputs and applies a low-pass filter to create a mono, low-frequency signal. Please refer to the target HybridFlows for details regarding the options for the serial data output.

8.3.4.1 BD-Modulation

The TAS5756M uses BD modulation. This modulation scheme allows operation without the classic LC output filter when the amp is driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage PVDD. The SPK_OUTx+ and SPK_OUTx- are in phase with each other with no input signal so that there is little or no current in the speaker. The duty cycle of SPK_OUTx+ is greater than 50% and SPK_OUTx- is less than 50% for positive output voltages. The duty cycle of SPK_OUTx+ is less than 50% and SPK_OUTx- is greater than 50% for negative output voltages. The voltage across the load remains at 0 V throughout most of the switching period, reducing the switching current, which reduces any I²R losses in the load.

Figure 71. BD-Modulation

8.3.5.1 HybridFlow Architecture

The Hybrid RAM and ROM Architecture allows the device to be highly flexible, but also easy to use. Unlike a device where all digital processing blocks are hard-coded in ROM, the hybrid RAM and ROM architecture allows a variety of processing blocks to be used in various combinations with various connectivity. These combinations of processing blocks are called HybridFlows.

HybridFlows are generated by combining a collection of processing blocks together in a targeted manner so that the device is well suited for a particular application or use case. Some HybridFlows are targeted for stereo applications, while others are targeted for mono, 1.1 (Bi-Amped), or 2.1 configurations.

It is important to note that the amount of processing which can be combined together into a given process flow is highly dependent on the sample rate of the audio signal which is being processed. For instance, an audio signal at 48 kHz can have much more processing applied than the same signal presented to the TAS5756M device at 192 kHz sample rate. For this reason, a HybridFlow which supports only up to 48 kHz sample rate cannot be used with a 192 kHz input signal.

8.3.5.2 Volume Control

8.3.5.2.1 Digital Volume Control

A basic digital volume control with range between 24 dB and 103 dB and mute is available on each channels by P0-R61-B[7:0] for SPK_OUTB± and P0-R62-B[7:0] for SPK_OUTA±. These volume controls all have 0.5 dB step programmability over most gain and attenuation ranges. Table 11 lists the detailed gain versus programmed setting for this basic volume control. Volume can be changed for both SPK_OUTB± and SPK_OUTA± at the same time or independently by P0-R61-B[1:0] . When B[1:0] set 00 (default), independent control is selected. When B[1:0] set 01, SPK_OUTA± accords with SPK_OUTB± volume. When B[1:0] set 10, SPK_OUTA± volume controls the volume for both channels. To set B[1:0] to 11 is prohibited.

Table 11. Digital Volume Control Settings

GAIN SETTING	BINARY DATA	GAIN (dB)	COMMENTS
0	0000-0000	24.0	Positive maximum
1	0000-0001	23.5
. . .	. . .	. . .
46	0010-1110	1.0
47	0010-1111	0.5
48	0011-0000	0.0	No attenuation (default)
49	0011-0001	–0.5
50	0011-0010	–1.0
51	0011-0011	–1.5
. . .	. . .	. . .
253	1111-1101	–102.5
254	1111-1110	–103	Negative maximum
255	1111-1111	–	Negative infinite (Mute)

Ramp-up frequency and ramp-down frequency can be controlled by P0-R63, B[7:6] and B[3:2] as shown in Table 12. Also ramp-up step and ramp-down step can be controlled by P0-R63, B[5:4] and B[1:0] as shown in Table 13.

Table 12. Ramp Up or Down Frequency

RAMP UP SPEED	EVERY N fS	COMMENTS	RAMP DOWN FREQUENCY	EVERY N fS	COMMENTS
00	1	Default	00	1	Default
01	2		01	2
10	4		10	4
11	Direct change		11	Direct change

Table 13. Ramp Up or Down Step

RAMP UP STEP	STEP dB	COMMENTS	RAMP DOWN STEP	STEP dB	COMMENTS
00	4.0		00	–4.0
01	2.0		01	–2.0
10	1.0	Default	10	–1.0	Default
11	0.5		11	–0.5

8.3.5.2.1.1 Emergency Volume Ramp Down

Emergency ramp down of the volume by is provided for situations such as I²S clock error and power supply failure. Ramp-down speed is controlled by P0-R64-B[7:6]. Ramp-down step can be controlled by P0-R64-B[5:4]. Default is ramp-down by every f_S cycle with –4dB step.

Table 14. Sample Rates vs Synchronization Signal

Table 15. Amplifier Switching Mode vs. SPK_GAIN/FREQ Voltage

8.3.7.1 Device Overtemperature Protection

The TAS5756M device continuously monitors die temperature to ensure it does to exceed the OTE_THRES level specified in the Recommended Operating Conditions table. If an OTE event occurs, the SPK_FAULT line is pulled low and out the SPK_OUTxx outputs transition to high impedance, signifying a fault. This is a non-latched error and will attempt to self clear after OTE_CLRTIME has passed.

8.3.7.2 SPK_OUTxx Overcurrent Protection

The TAS5756M device continuously monitors the output current of each amplifier output to ensure it does to exceed the OCE_THRES level specified in the Recommended Operating Conditions table. If an OCE event occurs, the SPK_FAULT line is pulled low and the SPK_OUTxx outputs transition to high impedance, signifying a fault. This is a non-latched error and will attempt to self clear after OCE_CLRTIME has passed.

8.3.7.3 DC Offset Protection

If the TAS5756M device measures a DC offset in the output voltage, the SPK_FAULT line is pulled low and the SPK_OUTxx outputs transition to high impedance, signifying a fault. This latched error require the SPK_MUTE line to toggle to reset the error. Alternatively, pulling the MCLK, SCLK, or LRCK low causes a clock error, which also resets the device. Normal operation resumes by re-starting the stopped clock.

8.3.7.4 Internal V_AVDD Undervoltage-Error Protection

The TAS5756M device internally monitors the AVDD net to protect against the AVDD supply dropping unexpectedly. To enable this feature, P1-R5-B0 is used.

8.3.7.5 Internal V_PVDD Undervoltage-Error Protection

If the voltage presented on the PVDD supply drops below the UVE_THRES(PVDD) value listed in the Recommended Operating Conditions table, the SPK_OUTxx outputs transition to high impedance. This is a self-clearing error, which means that once the PVDD level drops below the level listed in the Recommended Operating Conditions table, the device resumes normal operation.

8.3.7.6 Internal V_PVDD Overvoltage-Error Protection

If the voltage presented on the PVDD supply exceeds the OVE_THRES(PVDD) value listed in the Recommended Operating Conditions table, the SPK_OUTxx outputs will transition to high impedance. This is a self-clearing error, which means that once the PVDD level drops below the level listed in the Recommended Operating Conditions table, the device will resume normal operation. It is important to note that this voltage only protects up to the level described in the Recommended Operating Conditions table for the PVDD voltage. Exceeding this absolute maximum rating causes damage and possible device failure, because the levels exceed that which can be protected against by the OVE protection circuit.

8.3.7.7 External Undervoltage-Error Protection

The SPK_MUTE pin can also be used to monitor a system voltage, such as a LCD TV backlight, a battery pack in portable device, by using a voltage divider created with two resistors (see Figure 72).

• If the SPK_MUTE pin makes a transition from 1 to 0 over 6 ms or more, the device switches into external undervoltage protection mode. This mode uses two trigger levels.
• When the SPK_MUTE pin level reaches 2 V, soft mute process begins.
• When the SPK_MUTE pin level reaches 1.2 V, analog output mute engages, regardless of digital audio level, and analog output shutdown begins.

Figure 73 shows a timing diagram for external undervoltage error protection.

When the divider is set correctly, any DC voltage can be monitored. Figure 72 shows a 12-V example of how the SPK_MUTE is used for external undervoltage error protection.

Figure 72. SPK_MUTE Used in External Undervoltage Error Protection

Figure 73. SPK_MUTE Timing for External Undervoltage Error Protection

8.3.7.8 Internal Clock Error Notification (CLKE)

8.3.9.1 Slave Address

The TAS5756M device has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset to 10011 (0x9x). The next two bits of the address byte are the device select bits which can be user-defined by the ADR1 and ADR0 terminals. A maximum of four devices can be connected on the same bus at one time. This gives a range of 0x98, 0x9A, 0x9C and 0x9E, as detailed below. Each TAS5756M device responds when it receives its own slave address.

8.3.9.2 Register Address Auto-Increment Mode

Figure 75. Auto Increment Mode

Auto-increment mode allows multiple sequential register locations to be written to or read back in a single operation, and is especially useful for block write and read operations.

8.3.9.3 Packet Protocol

A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data if write or acknowledge if read, and stop condition. The TAS5756M device supports only slave receivers and slave transmitters.

Figure 76. Packet Protocol

M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition

8.3.9.4 Write Register

A master can write to any TAS5756M device registers using single or multiple accesses. The master sends a TAS5756M device slave address with a write bit, a register address with auto-increment bit, and the data. If auto-increment is enabled, the address is that of the starting register, followed by the data to be transferred. When the data is received properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 20 shows the write operation.

M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition; W = Write; ACK = Acknowledge

8.3.9.5 Read Register

A master can read the TAS5756M device register. The value of the register address is stored in an indirect index register in advance. The master sends a TAS5756M device slave address with a read bit after storing the register address. Then the TAS5756M device transfers the data which the index register points to. When auto-increment is enabled, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 21 lists the read operation.

M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated start condition; Sp = Stop Condition; W = Write; R = Read; NACK = Not acknowledge

8.4.4.1 Stereo Mode

The familiar stereo mode of operation uses the TAS5756M device to amplify two independent signals, which represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented on differential output pairs shown as SPK_OUTA± and SPK_OUTB±. The routing of the audio data which is presented on the SPK_OUTxx outputs can be changed according to the HybridFlow which is used and the configuration of registers P0-R42-B[5:4] and P0-R42-B[1:0]. This mode of operation is shown in Figure 79.

By default, the TAS5756M device is configured to output the Right frame of a I²S input on the Channel A output and the left frame on the Channel B output.

8.4.4.2 Mono Mode

This mode of operation is used to describe operation in which the two outputs of the device are placed in parallel with one another to increase the power sourcing capabilities of the device.

On the output side of the TAS5756M device, the summation of the devices can be done before the filter in a configuration called Pre-Filter Parallel Bridge Tied Load (PBTL). However, it is sometimes preferable to merge the two outputs together after the inductor portion of the output filter. Doing so does require two additional inductors, but allows smaller, less expensive inductors to be used because the current is divided between the two inductors. This is called Post-Filter PBTL. Both variants of mono operation are shown in Figure 77 and Figure 78.

Figure 77. Pre-Filter PBTL

Figure 78. Post-Filter PBTL

On the input side of the TAS5756M device, the input signal to the mono amplifier can be selected from the any slot in a TDM stream or the left or right frame from an I²S, LJ, or RJ signal. It can also be configured to amplify some mixture of two signals, as in the case of a subwoofer channel which mixes the left and right channel together and sends it through a low-pass filter to create a mono, low-frequency signal.

This mode of operation is shown in the Mono (PBTL) Systems section.

8.4.4.3 Bi-Amp Mode

Bi-Amp mode, sometimes also referred to as 1.1 Mode uses a two channel device (such as the TAS5756M device ) to amplify two different frequency regions of the same signal for a two-way speaker. This is most often used in a single active speaker, where one channel of the amplifier is use to drive the high frequency transducer and one channel is used to drive the low-frequency transducer. To operate in Bi-Amped Mode or 1.1 Mode, an appropriate HybridFlow must be selected, because the frequency separation and audio processing must occur in the DSP. This mode of operation is shown in the 1.1 (Dual BTL, Bi-Amped) Systems section.

8.4.4.4 Master and Slave Mode Clocking for Digital Serial Audio Port

The digital audio serial port in the TAS5756M device can be configured to receive its clocks from another device as a serial audio slave device. This mode of operation is described in the Clock Slave Mode with SLCK PLL to Generate Internal Clocks (3-Wire PCM) section. If there no system processor available to provide the audio clocks, the TAS5756M device can be placed into Master Mode. In this mode, the TAS5756M device provides the clocks to the other audio devices in the system. For more details regarding the Master and Slave mode operation within the TAS5756M device, see the Serial Audio Port Operating Modes section.