ZHCSBC3F July 2013 – February 2020 TAS5760M
PRODUCTION DATA.
I²S timing uses LRCK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCK is LOW for the left channel and HIGH for the right channel. A bit clock, called SCLK, runs at 32, 48, or 64 × fS and is used to clock in the data. There is a delay of one bit clock from the time the LRCK signal changes state to the first bit of data on the data lines. The data is presented in 2's-complement form (MSB-first) and is valid on the rising edge of bit clock.