ZHCSDC1D September   2013  – October 2018 TAS5766M , TAS5768M

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      智能放大器概览
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Electrical Characteristics
    8. 6.8 Timing Requirements - I2C Bus Timing
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart SOA
      2. 7.3.2 Smart BASS
      3. 7.3.3 Smart Protection
      4. 7.3.4 Implementing a Real World Design
      5. 7.3.5 Modulation Schemes
        1. 7.3.5.1 BD-Modulation
        2. 7.3.5.2 1SPW-Modulation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Protection System
        1. 7.4.1.1 Over Current Protection
        2. 7.4.1.2 Thermal Protection
        3. 7.4.1.3 DC Protection
      2. 7.4.2 Reset and System Clock Functions
        1. 7.4.2.1 Power-On Reset Function
        2. 7.4.2.2 System Clock Input
      3. 7.4.3 System Clock PLL Mode
      4. 7.4.4 Clock Generation and PLL
      5. 7.4.5 PLL Calculation
      6. 7.4.6 Audio Data Interface
        1. 7.4.6.1 Audio Serial Interface
        2. 7.4.6.2 PCM Audio Data Formats and Timing
      7. 7.4.7 TAS576xM Audio Processing Options
        1. 7.4.7.1  Overview
        2. 7.4.7.2  miniDSP Instruction Register
        3. 7.4.7.3  Digital Output
        4. 7.4.7.4  Software
        5. 7.4.7.5  Process Flow
        6. 7.4.7.6  Zero Data Detect
        7. 7.4.7.7  Power Save Modes
        8. 7.4.7.8  XSMT Pin (Soft Mute/Soft Un-Mute)
        9. 7.4.7.9  External Power Sense Undervoltage Protection Mode
        10. 7.4.7.10 Recommended Power Down Sequence
          1. 7.4.7.10.1 XSMT = 0
          2. 7.4.7.10.2 Clock Error Detect
          3. 7.4.7.10.3 Planned Shutdown
    5. 7.5 Programming
      1. 7.5.1 I2C Interface and Slave Address
      2. 7.5.2 Slave Address
      3. 7.5.3 Register Address Auto-Increment Mode
      4. 7.5.4 Packet Protocol
        1. Table 18. Read / Write Operation – Basic I2C Framework
      5. 7.5.5 Write Register
        1. Table 19. Write Operation
        2. 7.5.5.1   Read Register
          1. Table 20. Read Operation
    6. 7.6 Register Maps
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection Criteria
      2. 8.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
      3. 8.1.3 Amplifier Output Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Gain Setting and Output Switch Frequency
          2. 8.2.1.2.2 Gain Setting and Supply Voltage
          3. 8.2.1.2.3 DAC to AMP AC Coupling
          4. 8.2.1.2.4 Bootstrap Capacitors
        3. 8.2.1.3 BTL Application Curves
      2. 8.2.2 Mono/PBTL Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 PBTL Application Curves
      3. 8.2.3 QFN BTL Application Diagram
        1. 8.2.3.1 Design Requirements
  9. 9 Power Supply Recommendations
    1. 9.1 AVDD, DVDD, CPVDD Supply
    2. 9.2 GVDD Supply
    3. 9.3 PVCC, AVCC Power Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Register Map Information
    1. 11.1 Detailed Register Map Descriptions
      1. 11.1.1 Register Map Summary
      2. 11.1.2 Page 0 Registers
        1. 11.1.2.1  Page 0 / Register 1 (Hex 0x01)
        2. 11.1.2.2  Page 0 / Register 2 (Hex 0x02)
        3. 11.1.2.3  Page 0 / Register 3 (Hex 0x03)
        4. 11.1.2.4  Page 0 / Register 4 (Hex 0x04)
        5. 11.1.2.5  Page 0 / Register 7 (Hex 0x07)
        6. 11.1.2.6  Page 0 / Register 8 (Hex 0x08)
        7. 11.1.2.7  Page 0 / Register 9 (Hex 0x09)
        8. 11.1.2.8  Page 0 / Register 10 (Hex 0x0A)
        9. 11.1.2.9  Page 0 / Register 12 (Hex 0x0C)
        10. 11.1.2.10 Page 0 / Register 13 (Hex 0x0D)
        11. 11.1.2.11 Page 0 / Register 20 (Hex 0x14)
        12. 11.1.2.12 Page 0 / Register 21 (Hex 0x15)
        13. 11.1.2.13 Page 0 / Register 22 (Hex 0x16)
        14. 11.1.2.14 Page 0 / Register 23 (Hex 0x17)
        15. 11.1.2.15 Page 0 / Register 24 (Hex 0x18)
        16. 11.1.2.16 Page 0 / Register 27 (Hex 0x1B)
        17. 11.1.2.17 Page 0 / Register 28 (Hex 0x1C)
        18. 11.1.2.18 Page 0 / Register 29 (Hex 0x1D)
        19. 11.1.2.19 Page 0 / Register 30 (Hex 0x1E)
        20. 11.1.2.20 Page 0 / Register 32 (Hex 0x20)
        21. 11.1.2.21 Page 0 / Register 33 (Hex 0x21)
        22. 11.1.2.22 Page 0 / Register 34 (Hex 0x22)
        23. 11.1.2.23 Page 0 / Register 35 (Hex 0x23)
        24. 11.1.2.24 Page 0 / Register 36 (Hex 0x24)
        25. 11.1.2.25 Page 0 / Register 37 (Hex 0x25)
        26. 11.1.2.26 Page 0 / Register 40 (Hex 0x28)
        27. 11.1.2.27 Page 0 / Register 41 (Hex 0x29)
        28. 11.1.2.28 Page 0 / Register 42 (Hex 0x2A)
        29. 11.1.2.29 Page 0 / Register 43 (Hex 0x2B)
        30. 11.1.2.30 Page 0 / Register 44 (Hex 0x2C)
        31. 11.1.2.31 Page 0 / Register 59 (Hex 0x3B)
        32. 11.1.2.32 Page 0 / Register 65 (Hex 0x41)
        33. 11.1.2.33 Page 0 / Register 66 (Hex 0x42)
        34. 11.1.2.34 Page 0 / Register 82 (Hex 0x52)
        35. 11.1.2.35 Page 0 / Register 83 (Hex 0x53)
        36. 11.1.2.36 Page 0 / Register 84 (Hex 0x54)
        37. 11.1.2.37 Page 0 / Register 85 (Hex 0x55)
        38. 11.1.2.38 Page 0 / Register 86 (Hex 0x56)
        39. 11.1.2.39 Page 0 / Register 87 (Hex 0x57)
        40. 11.1.2.40 Page 0 / Register 90 (Hex 0x5A)
        41. 11.1.2.41 Page 0 / Register 91 (Hex 0x5B)
        42. 11.1.2.42 Page 0 / Register 92 (Hex 0x5C)
        43. 11.1.2.43 Page 0 / Register 93 (Hex 0x5D)
        44. 11.1.2.44 Page 0 / Register 94 (Hex 0x5E)
        45. 11.1.2.45 Page 0 / Register 95 (Hex 0x5F)
        46. 11.1.2.46 Page 0 / Register 108 (Hex 0x6C)
        47. 11.1.2.47 Page 0 / Register 118 (Hex 0x76)
        48. 11.1.2.48 Page 0 / Register 119 (Hex 0x77)
        49. 11.1.2.49 Page 0 / Register 120 (Hex 0x78)
        50. 11.1.2.50 Page 0 / Register 121 (Hex 0x79)
      3. 11.1.3 Page 1 Registers
        1. 11.1.3.1 Page 1 / Register 2 (Hex 0x02)
        2. 11.1.3.2 Page 1 / Register 5 (Hex 0x05)
        3. 11.1.3.3 Page 1 / Register 6 (Hex 0x06)
        4. 11.1.3.4 Page 1 / Register 7 (Hex 0x07)
        5. 11.1.3.5 Page 1 / Register 8 (Hex 0x08)
      4. 11.1.4 Page 44 Registers
        1. 11.1.4.1 Page 44 / Register 1 (Hex 0x01)
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.4.6.2 PCM Audio Data Formats and Timing

The TAS576xM supports industry-standard audio data formats, including standard I2S and left-justified. Data formats are selected via Register (Pg0Reg40). All formats require binary 2s-complement, MSB-first audio data, up to 32-bit audio data is accepted.

The TAS576xM also supports right-justified and TDM. I2S, LJ, RJ, and TDM are selected using Register (Pg0Reg40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are accepted. Default setting is I2S and 24 bit word length. The I2S slave timing is shown in Figure 35.

TAS5766M TAS5768M ser_aud_tim_SLAS965.gifFigure 35. TAS576xM Serial Audio Timing – Slave

Table 10. Audio Interface Slave Timing

MIN MAX UNIT
tBCY BCLK pulse Cycle Time 40 ns
tBCL BCLK pulse Width LOW 16 ns
tBCH BCLK pulse Width HIGH 16 ns
tBL BCLK Rising Edge to LRCLK Edge 8 ns
tBCLK BCLK frequency at DVDD = 3.3V 24.576 MHz
tLB LRCLK Edge to BCLK Rising Edge 8 ns
tDS DATA set Up time 8 ns
tDH DATA Hold Time 8 ns
tDOD DATA delay time from BCLK falling edge 15 ns

The TAS576xM can act as an I2S master, generating BCLK and LRCLK as outputs from the SCLK input.

Table 11. I2S Master Mode Registers

REGISTER FUNCTION
Page 0, register 9, D(0), D(4) and D85) I2S master Mode select
Register 32, D(6:0) BCLK divider and LRCLK divider
Register 33, D(7:0)

The I2S master timing is shown in Figure 36 and Table 12.

TAS5766M TAS5768M ser_aud_tim_master_SLAS965.gifFigure 36. TAS576xM Serial Audio Timing - Master

Table 12. Audio Interface Master Timing

MIN MAX UNIT
tBCY BCLK pulse Cycle Time 40 ns
tBCL BCLK pulse Width LOW 16 ns
tBCH BCLK pulse Width HIGH 16 ns
tBL BCLK Rising Edge to LRCLK Edge 8 ns
tBCLK BCLK frequency at DVDD = 3.3V 24.576 MHz
tLB LRCLK Edge to BCLK Rising Edge 8 ns
tDS DATA set Up time 8 ns
tDH DATA Hold Time 8 ns
tDOD DATA delay time from BCLK falling edge 15 ns
TAS5766M TAS5768M left_just_aud_data_for_SLAS965.gifFigure 37. Left Justified Audio Data Format
TAS5766M TAS5768M I2S_aud_data_for_SLAS965.gifFigure 38. I2S Audio Data Format
TAS5766M TAS5768M right_just_aud_data_for_SLAS965.gifFigure 39. Right Justified Audio Data Format
TAS5766M TAS5768M TDM_aud_data_for_SLAS965.gifFigure 40. TDM Audio Data Format
TAS5766M TAS5768M TDM_aud_data_for_2_SLAS965.gifFigure 41. TDM 2 Audio Data Format
TAS5766M TAS5768M TDM_aud_data_for_3_SLAS965.gifFigure 42. TDM 3 Audio Data Format
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