7.4.4 Clock Generation and PLL

The TAS576xM supports a wide range of options to generate the required clocks for the DAC section as well as interface and other control blocks as shown in Figure 34.

The clocks for the PLL require a source reference clock. This clock is sourced as the incoming BCLK or SCLK. The source reference clock for the PLL reference clock is selected by programming the SRCREF value on Page 0, Register 13, D(6:4). The PLL reference clock can then be routed through highly-flexible clock dividers shown in Table 5 to generate the various clocks required for the DAC, Negative Charge Pump (NCP), Internal modulator and sections. The TAS576xM provides several programmable clock dividers to achieve a variety of sampling rates for the DAC and clocks for the NCP, OSR, and the OSRCK for OSR must be set at 16fS frequency by DOSR on Page0, Register 30, D(6:0).

If PLL functionality isn’t required, set the PLLEN value on Page 0, Register 4, D(0) to 0. In this situation, an external SCLK is required.

Figure 34. PLL Clock Source and Clock Distribution