ZHCSGH3A March   2016  – July 2017 TAS5782M

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化框图
      2. 10% THD+N 时的功率与 PVDD 间的关系 (1)
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Internal Pin Configurations
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power Dissipation Characteristics
    7. 7.7  MCLK Timing
    8. 7.8  Serial Audio Port Timing – Slave Mode
    9. 7.9  Serial Audio Port Timing – Master Mode
    10. 7.10 I2C Bus Timing – Standard
    11. 7.11 I2C Bus Timing – Fast
    12. 7.12 SPK_MUTE Timing
    13. 7.13 Typical Characteristics
      1. 7.13.1 Bridge Tied Load (BTL) Configuration Curves
      2. 7.13.2 Parallel Bridge Tied Load (PBTL) Configuration
  8. 8 Parametric Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-on-Reset (POR) Function
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port
        1. 9.3.3.1 Clock Master Mode from Audio Rate Master Clock
        2. 9.3.3.2 Clock Master from a Non-Audio Rate Master Clock
        3. 9.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
        4. 9.3.3.4 Clock Slave Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM)
          1. 9.3.3.4.1 Clock Generation using the PLL
          2. 9.3.3.4.2 PLL Calculation
            1. 9.3.3.4.2.1 Examples:
        5. 9.3.3.5 Serial Audio Port – Data Formats and Bit Depths
          1. 9.3.3.5.1 Data Formats and Master/Slave Modes of Operation
        6. 9.3.3.6 Input Signal Sensing (Power-Save Mode)
      4. 9.3.4 Enable Device
        1. 9.3.4.1 Example
      5. 9.3.5 Volume Control
        1. 9.3.5.1 DAC Digital Gain Control
          1. 9.3.5.1.1 Emergency Volume Ramp Down
      6. 9.3.6 Adjustable Amplifier Gain and Switching Frequency Selection
      7. 9.3.7 Error Handling and Protection Suite
        1. 9.3.7.1 Device Overtemperature Protection
        2. 9.3.7.2 SPK_OUTxx Overcurrent Protection
        3. 9.3.7.3 DC Offset Protection
        4. 9.3.7.4 Internal VAVDD Undervoltage-Error Protection
        5. 9.3.7.5 Internal VPVDD Undervoltage-Error Protection
        6. 9.3.7.6 Internal VPVDD Overvoltage-Error Protection
        7. 9.3.7.7 External Undervoltage-Error Protection
        8. 9.3.7.8 Internal Clock Error Notification (CLKE)
      8. 9.3.8 GPIO Port and Hardware Control Pins
      9. 9.3.9 I2C Communication Port
        1. 9.3.9.1 Slave Address
        2. 9.3.9.2 Register Address Auto-Increment Mode
        3. 9.3.9.3 Packet Protocol
        4. 9.3.9.4 Write Register
        5. 9.3.9.5 Read Register
        6. 9.3.9.6 DSP Book, Page, and Register Update
          1. 9.3.9.6.1 Book and Page Change
          2. 9.3.9.6.2 Swap Flag
          3. 9.3.9.6.3 Example Use
    4. 9.4 Device Functional Modes
      1. 9.4.1 Serial Audio Port Operating Modes
      2. 9.4.2 Communication Port Operating Modes
      3. 9.4.3 Speaker Amplifier Operating Modes
        1. 9.4.3.1 Stereo Mode
        2. 9.4.3.2 Mono Mode
        3. 9.4.3.3 Master and Slave Mode Clocking for Digital Serial Audio Port
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 External Component Selection Criteria
      2. 10.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
      3. 10.1.3 Amplifier Output Filtering
      4. 10.1.4 Programming the TAS5782M
        1. 10.1.4.1 Resetting the TAS5782M Registers and Modules
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Step One: Hardware Integration
          2. 10.2.1.2.2 Step Two: System Level Tuning
          3. 10.2.1.2.3 Step Three: Software Integration
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Mono (PBTL) Systems
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Step One: Hardware Integration
          2. 10.2.2.2.2 Step Two: System Level Tuning
          3. 10.2.2.2.3 Step Three: Software Integration
        3. 10.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems
      3. 10.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems
        1. 10.2.3.1 Advanced 2.1 System (Two TAS5782M devices)
        2. 10.2.3.2 Design Requirements
        3. 10.2.3.3 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 DVDD Supply
      2. 11.1.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB footprint and Via Arrangement
            1. 12.1.3.2.1.1 Solder Stencil
    2. 12.2 Layout Example
      1. 12.2.1 2.0 (Stereo BTL) System
      2. 12.2.2 Mono (PBTL) System
      3. 12.2.3 2.1 (Stereo BTL + Mono PBTL) Systems
  13. 13Register Maps
    1. 13.1 Registers - Page 0
      1. 13.1.1  Register 1 (0x01)
        1. Table 27. Register 1 (0x01) Field Descriptions
        2. Table 28. Register 2 (0x02) Field Descriptions
        3. Table 29. Register 3 (0x03) Field Descriptions
        4. Table 30. Register 4 (0x04) Field Descriptions
      2. 13.1.2  Register 6 (0x06)
        1. Table 31. Register 6 (0x06) Field Descriptions
      3. 13.1.3  Register 7 (0x07)
        1. Table 32. Register 7 (0x07) Field Descriptions
      4. 13.1.4  Register 8 (0x08)
        1. Table 33. Register 8 (0x08) Field Descriptions
      5. 13.1.5  Register 9 (0x09)
        1. Table 34. Register 9 (0x09) Field Descriptions
      6. 13.1.6  Register 12 (0x0C)
        1. Table 35. Register 12 (0x0C) Field Descriptions
      7. 13.1.7  Register 13 (0x0D)
        1. Table 36. Register 13 (0x0D) Field Descriptions
      8. 13.1.8  Register 14 (0x0E)
        1. Table 37. Register 14 (0x0E) Field Descriptions
      9. 13.1.9  Register 15 (0x0F)
        1. Table 38. Register 15 (0x0F) Field Descriptions
      10. 13.1.10 Register 16 (0x10)
        1. Table 39. Register 16 (0x10) Field Descriptions
      11. 13.1.11 Register 17 (0x11)
        1. Table 40. Register 17 (0x11) Field Descriptions
      12. 13.1.12 Register 18 (0x12)
        1. Table 41. Register 18 (0x12) Field Descriptions
      13. 13.1.13 Register 20 (0x14)
        1. Table 42. Register 20 (0x14) Field Descriptions
      14. 13.1.14 Register 21 (0x15)
        1. Table 43. Register 21 (0x15) Field Descriptions
      15. 13.1.15 Register 22 (0x16)
        1. Table 44. Register 22 (0x16) Field Descriptions
      16. 13.1.16 Register 23 (0x17)
        1. Table 45. Register 23 (0x17) Field Descriptions
      17. 13.1.17 Register 24 (0x18)
        1. Table 46. Register 24 (0x18) Field Descriptions
      18. 13.1.18 Register 27 (0x1B)
        1. Table 47. Register 27 (0x1B) Field Descriptions
      19. 13.1.19 Register 28 (0x1C)
        1. Table 48. Register 28 (0x1C) Field Descriptions
      20. 13.1.20 Register 29 (0x1D)
        1. Table 49. Register 29 (0x1D) Field Descriptions
      21. 13.1.21 Register 30 (0x1E)
        1. Table 50. Register 30 (0x1E) Field Descriptions
      22. 13.1.22 Register 32 (0x20)
        1. Table 51. Register 32 (0x20) Field Descriptions
      23. 13.1.23 Register 33 (0x21)
        1. Table 52. Register 33 (0x21) Field Descriptions
      24. 13.1.24 Register 34 (0x22)
        1. Table 53. Register 34 (0x22) Field Descriptions
      25. 13.1.25 Register 37 (0x25)
        1. Table 54. Register 37 (0x25) Field Descriptions
      26. 13.1.26 Register 40 (0x28)
        1. Table 55. Register 40 (0x28) Field Descriptions
      27. 13.1.27 Register 41 (0x29)
        1. Table 56. Register 41 (0x29) Field Descriptions
      28. 13.1.28 Register 42 (0x2A)
        1. Table 57. Register 42 (0x2A) Field Descriptions
      29. 13.1.29 Register 43 (0x2B)
        1. Table 58. Register 43 (0x2B) Field Descriptions
      30. 13.1.30 Register 44 (0x2C)
        1. Table 59. Register 44 (0x2C) Field Descriptions
      31. 13.1.31 Register 59 (0x3B)
        1. Table 60. Register 59 (0x3B) Field Descriptions
      32. 13.1.32 Register 60 (0x3C)
        1. Table 61. Register 60 (0x3C) Field Descriptions
      33. 13.1.33 Register 61 (0x3D)
        1. Table 62. Register 61 (0x3D) Field Descriptions
      34. 13.1.34 Register 62 (0x3E)
        1. Table 63. Register 62 (0x3E) Field Descriptions
      35. 13.1.35 Register 63 (0x3F)
        1. Table 64. Register 63 (0x3F) Field Descriptions
      36. 13.1.36 Register 64 (0x40)
        1. Table 65. Register 64 (0x40) Field Descriptions
      37. 13.1.37 Register 65 (0x41)
        1. Table 66. Register 65 (0x41) Field Descriptions
      38. 13.1.38 Register 67 (0x43)
        1. Table 67. Register 67 (0x43) Field Descriptions
      39. 13.1.39 Register 68 (0x44)
        1. Table 68. Register 68 (0x44) Field Descriptions
      40. 13.1.40 Register 69 (0x45)
        1. Table 69. Register 69 (0x45) Field Descriptions
      41. 13.1.41 Register 70 (0x46)
        1. Table 70. Register 70 (0x46) Field Descriptions
      42. 13.1.42 Register 71 (0x47)
        1. Table 71. Register 71 (0x47) Field Descriptions
      43. 13.1.43 Register 72 (0x48)
        1. Table 72. Register 72 (0x48) Field Descriptions
      44. 13.1.44 Register 73 (0x49)
        1. Table 73. Register 73 (0x49) Field Descriptions
      45. 13.1.45 Register 74 (0x4A)
        1. Table 74. Register 74 (0x4A) Field Descriptions
      46. 13.1.46 Register 75 (0x4B)
        1. Table 75. Register 75 (0x4B) Field Descriptions
      47. 13.1.47 Register 76 (0x4C)
        1. Table 76. Register 76 (0x4C) Field Descriptions
      48. 13.1.48 Register 78 (0x4E)
        1. Table 77. Register 78 (0x4E) Field Descriptions
      49. 13.1.49 Register 79 (0x4F)
        1. Table 78. Register 79 (0x4F) Field Descriptions
      50. 13.1.50 Register 83 (0x53)
        1. Table 79. Register 83 (0x53) Register Field Descriptions
      51. 13.1.51 Register 85 (0x55)
        1. Table 80. Register 85 (0x55) Register Field Descriptions
      52. 13.1.52 Register 86 (0x56)
        1. Table 81. Register 86 (0x56) Register Field Descriptions
      53. 13.1.53 Register 87 (0x57)
        1. Table 82. Register 87 (0x57) Field Descriptions
      54. 13.1.54 Register 88 (0x58)
        1. Table 83. Register 88 (0x58) Field Descriptions
      55. 13.1.55 Register 91 (0x5B)
        1. Table 84. Register 91 (0x5B) Field Descriptions
      56. 13.1.56 Register 92 (0x5C)
        1. Table 85. Register 92 (0x5C) Field Descriptions
      57. 13.1.57 Register 93 (0x5D)
        1. Table 86. Register 93 (0x5D) Field Descriptions
      58. 13.1.58 Register 94 (0x5E)
        1. Table 87. Register 94 (0x5E) Field Descriptions
      59. 13.1.59 Register 95 (0x5F)
        1. Table 88. Register 95 (0x5F) Field Descriptions
      60. 13.1.60 Register 108 (0x6C)
        1. Table 89. Register 108 (0x6C) Field Descriptions
      61. 13.1.61 Register 119 (0x77)
        1. Table 90. Register 119 (0x77) Field Descriptions
      62. 13.1.62 Register 120 (0x78)
        1. Table 91. Register 120 (0x78) Field Descriptions
    2. 13.2 Registers - Page 1
      1. 13.2.1 Register 1 (0x01)
        1. Table 92. Register 1 (0x01) Field Descriptions
      2. 13.2.2 Register 2 (0x02)
        1. Table 93. Register 2 (0x02) Field Descriptions
      3. 13.2.3 Register 6 (0x06)
        1. Table 94. Register 6 (0x06) Field Descriptions
      4. 13.2.4 Register 7 (0x07)
        1. Table 95. Register 7 (0x07) Field Descriptions
      5. 13.2.5 Register 9 (0x09)
        1. Table 96. Register 9 (0x09) Field Descriptions
  14. 14器件和文档支持
    1. 14.1 器件支持
      1. 14.1.1 器件命名规则
      2. 14.1.2 开发支持
    2. 14.2 接收文档更新通知
    3. 14.3 社区资源
    4. 14.4 商标
    5. 14.5 静电放电警告
    6. 14.6 Glossary
  15. 15机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5782MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to 768 kHz unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL I/O
|IIH|1 Input logic high current level for DVDD referenced digital input pins(2) VIN(DigIn) = VDVDD 10 µA
|IIL|1 Input logic low current level for DVDD referenced digital input pins(2) VIN(DigIn) = 0 V –10 µA
VIH1 Input logic high threshold for DVDD referenced digital inputs(2) 70% VDVDD
VIL1 Input logic low threshold for DVDD referenced digital inputs(2) 30% VDVDD
VOH(DigOut) Output logic high voltage level(2) IOH = 4 mA 80% VDVDD
VOL(DigOut) Output logic low voltage level(2) IOH = –4 mA 22% VDVDD
VOL(SPK_FAULT) Output logic low voltage level for SPK_FAULT With 100-kΩ pullup resistor 0.8 V
GVDD_REG GVDD regulator voltage 7 V
I2C CONTROL PORT
CL(I2C) Allowable load capacitance for each I2C Line 400 pF
fSCL(fast) Support SCL frequency No wait states, fast mode 400 kHz
fSCL(slow) Support SCL frequency No wait states, slow mode 100 kHz
VNH Noise margin at High level for each connected device (including hysteresis) 0.2 × VDD V
MCLK AND PLL SPECIFICATIONS
DMCLK Allowable MCLK duty cycle 40% 60%
fMCLK Supported MCLK frequencies Up to 50 MHz 128 512 fS(1)
fPLL PLL input frequency Clock divider uses fractional divide
D > 0, P = 1		 6.7 20 MHz
Clock divider uses integer divide
D = 0, P = 1		 1 20
SERIAL AUDIO PORT
tDLY Required LRCK/FS to SCLK rising edge delay 5 ns
DSCLK Allowable SCLK duty cycle 40% 60%
fS Supported input sample rates 8 96 kHz
fSCLK Supported SCLK frequencies 32 64 fS(1)
fSCLK SCLK frequency Either master mode or slave mode 24.576 MHz
SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)
AV(SPK_AMP) Speaker amplifier gain SPK_GAIN/FREQ voltage < 3 V,
see Adjustable Amplifier Gain and Switching Frequency Selection 		20 dBV
SPK_GAIN/FREQ voltage > 3.3 V,
see Adjustable Amplifier Gain and Switching Frequency Selection 		26
ΔAV(SPK_AMP) Typical variation of speaker amplifier gain ±1 dBV
fSPK_AMP Switching frequency of the speaker amplifier Switching frequency depends on voltage presented at SPK_GAIN/FREQ pin and the clocking arrangement, including the incoming sample rate, see Adjustable Amplifier Gain and Switching Frequency Selection 176.4 768 kHz
KSVR Power supply rejection ratio Injected Noise = 50 Hz to 60 Hz, 200 mVP-P, Gain = 26 dB, input audio signal = digital zero 60 dB
rDS(on) Drain-to-source on resistance of the individual output MOSFETs VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C, includes PVDD/PGND pins, leadframe, bondwires and metallization layers. 120 mΩ
VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C 90
OCETHRES SPK_OUTxx overcurrent error threshold 7.5 A
OTETHRES Overtemperature error threshold 165 °C
OCECLRTIME Time required to clear overcurrent error after error condition is removed. 1.3 s
OTECLRTIME Time required to clear overtemperature error after error condition is removed. 1.3 s
OVETHRES(PVDD) PVDD overvoltage error threshold 27 V
UVETHRES(PVDD) PVDD undervoltage error threshold 4.3 V
SPEAKER AMPLIFIER (STEREO BTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 20 dB gain, VPVDD = 12 V 2 mV
Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 26 dB gain, VPVDD = 24 V 5 15
ICN(SPK) Idle channel noise VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 8 Ω, A-Weighted 49 µVRMS
VPVDD = 15 V, SPK_GAIN = 20 dB, RSPK = 8 Ω, A-Weighted 59
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, A-Weighted 81
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, A-Weighted 82
PO(SPK) Output Power (Per Channel) VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 4 Ω, THD+N = 0.1% 14 W
VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 8 Ω, THD+N = 0.1% 8
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 4 Ω, THD+N = 0.1% 23
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, THD+N = 0.1% 13
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 4 Ω, THD+N = 0.1% 34
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, THD+N = 0.1% 20
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 4 Ω, THD+N = 0.1% 40
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, THD+N = 0.1% 33
SNR Signal-to-noise ratio (referenced to 0 dBFS input signal) VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 103 dB
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 102
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 103
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 105
THD+NSPK Total harmonic distortion and noise VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 4 Ω, PO = 1 W, f = 1kHz 0.021%
VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 8 Ω, PO = 1 W, f = 1kHz 0.022%
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 4 Ω, PO = 1 W, f = 1kHz 0.02%
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, PO = 1 W, f = 1kHz 0.037%
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 4 Ω, PO = 1 W, f = 1kHz 0021%
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, PO = 1 W, f = 1kHz 0.028%
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 4 Ω, PO = 1 W, f = 1kHz 0.027%
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, PO = 1 W, f = 1kHz 0.038%
X-talkSPK Cross-talk (worst case between left-to-right and right-to-left coupling) VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 8 Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)		 –90 dB
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)		 –102
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)		 –93
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)		 –93
SPEAKER AMPLIFIER (MONO PBTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 20 dB gain, VPVDD = 12 V 0.7 mV
Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 26 dB gain, VPVDD = 24 V 4
ICN Idle channel noise VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 8 Ω, A-Weighted 48 µVRMS
VPVDD = 15 V, SPK_GAIN = 20 dB, RSPK = 8 Ω, A-Weighted 49
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, A-Weighted 83
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, A-Weighted 82
PO Output power (per channel) VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted 30 W
VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 16
VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 8 Ω, THD+N = 0.1% 9
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted 44
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 22
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, THD+N = 0.1% 13
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted 50
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 36
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, THD+N = 0.1% 20
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted 40
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted 61
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, THD+N = 0.1% 34
SNR Signal-to-noise ratio
(referenced to 0 dBFS input signal)		 VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 105 dB
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 104
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 105
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, A-Weighted, –120 dBFS Input 107
THD+N Total harmonic distortion and noise VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 2 Ω, PO = 1 W, f = 1kHz 0.014%
VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 4 Ω, PO = 1 W, f = 1kHz 0.011%
VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK = 8 Ω, PO = 1 W, f = 1kHz 0.014%
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 2 Ω, PO = 1 W, f = 1kHz 0.015%
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 4 Ω, PO = 1 W, f = 1kHz 0.013%
VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, PO = 1 W, f = 1kHz 0.015%
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 2 Ω, PO = 1 W, f = 1kHz 0.018%
V, RSPK = 4 Ω, PO = 1 W, f = 1kHz 0.012%
VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, PO = 1 W, f = 1kHz 0.020%
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 2 Ω, PO = 1 W, f = 1kHz 0.028%
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 4 Ω, PO = 1 W, f = 1kHz 0.02%
VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK = 8 Ω, PO = 1 W, f = 1kHz 0.027%
(1) A unit of fS indicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the TAS5782M device.
(2) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO2, LRCK/FS, MCLK,RESET, SCL, SCLK, SDA, SDIN, and SPK_MUTE.
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