米6体育平台手机版

ZHCSI92D May 2018 – November 2020 TAS5805M

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7.6.1 CONTROL PORT Registers

Table 7-6 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in Table 7-6 should be considered as reserved locations and the register contents should not be modified.

Table 7-6 CONTROL PORT Registers

Offset	Acronym	Register Name	Section
1h	RESET_CTRL	Register 1	Go
2h	DEVICE_CTRL_1	Register 2	Go
3h	DEVICE_CTRL_2	Register 3	Go
Fh	I2C_PAGE_AUTO_INC	Register 15	Go
28h	SIG_CH_CTRL	Register 40	Go
29h	CLOCK_DET_CTRL	Register 41	Go
30h	SDOUT_SEL	Register 48	Go
31h	I2S_CTRL	Register 49	Go
33h	SAP_CTRL1	Register 51	Go
34h	SAP_CTRL2	Register 52	Go
35h	SAP_CTRL3	Register 53	Go
37h	FS_MON	Register 55	Go
38h	BCK_MON	Register 56	Go
39h	CLKDET_STATUS	Register 57	Go
4Ch	DIG_VOL_CTRL	Register 76	Go
4Eh	DIG_VOL_CTRL2	Register 78	Go
4Fh	DIG_VOL_CTRL3	Register 79	Go
50h	AUTO_MUTE_CTRL	Register 80	Go
51h	AUTO_MUTE_TIME	Register 81	Go
53h	ANA_CTRL	Register 83	Go
54h	AGAIN	Register 84	Go
5Ch	BQ_WR_CTRL1	Register 92	Go
5Dh	DAC_CTRL	Register 93	Go
60h	ADR_PIN_CTRL	Register 96	Go
61h	ADR_PIN_CONFIG	Register 97	Go
66h	DSP_MISC	Register 102	Go
67h	DIE_ID	Register 103	Go
68h	POWER_STATE	Register 104	Go
69h	AUTOMUTE_STATE	Register 105	Go
6Ah	PHASE_CTRL	Register 106	Go
6Bh	SS_CTRL0	Register 107	Go
6Ch	SS_CTRL1	Register 108	Go
6Dh	SS_CTRL2	Register 109	Go
6Eh	SS_CTRL3	Register 110	Go
6Fh	SS_CTRL4	Register 111	Go
70h	CHAN_FAULT	Register 112	Go
71h	GLOBAL_FAULT1	Register 113	Go
72h	GLOBAL_FAULT2	Register 114	Go
73h	OT WARNING	Register 115	Go
74h	PIN_CONTROL1	Register 116	Go
75h	PIN_CONTROL2	Register 117	Go
76h	MISC_CONTROL	Register 118	Go
78h	FAULT_CLEAR	Register 120	Go

Complex bit access types are encoded to fit into small table cells. Table 7-7 shows the codes that are used for access types in this section.

Table 7-7 CONTROL PORT Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

7.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]

RESET_CTRL is shown in Figure 7-16 and described in Table 7-8.

Return to Summary Table.

Figure 7-16 RESET_CTRL Register

7	6	5	4	3	2	1	0
RESERVED			RST_MOD	RESERVED			RST_REG
R/W			W	R			W

Table 7-8 RESET_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	000	This bit is reserved
4	RST_MOD	W	0	WRITE CLEAR BIT Reset Modules WRITE CLEAR BIT Reset full digital core This bit resets full digital signal chain (Include DSP and Control Port Registers). Since the DSP is also reset, the coeffient RAM content will also be cleared by the DSP. 0: Normal 1: Reset modules
3-1	RESERVED	R	000	This bit is reserved
0	RST_CONTROL_REG	W	0	WRITE CLEAR BIT Reset Registers This bit resets the control port registers back to their initial values. The RAM content is not cleared. 0: Normal 1: Reset control port registers

7.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]

DEVICE_CTRL_1 is shown in Figure 7-17 and described in Table 7-9.

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Figure 7-17 DEVICE_CTRL_1 Register

7	6	5	4	3	2	1	0
RESERVED	FSW_SEL			RESERVED	DAMP_PBTL	DAMP_MOD
R/W	R/W			R/W	R/W	R/W

Table 7-9 DEVICE_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0	This bit is reserved
6-4	FSW_SEL	R/W	000	SELECT FSW 000:768K 001:384K 011:480K 100:576K 010:Reserved 101:Reserved 110:Reserved 111:Reserved
3	RESERVED	R/W	0	This bit is reserved
2	DAMP_PBTL	R/W	0	0: SET DAMP TO BTL MODE 1: SET DAMP TO PBTL MODE
1-0	DAMP_MOD	R/W	00	00:BD MODE 01:1SPW MODE 10:HYBRID MODE

7.6.1.3 DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]

DEVICE_CTRL_2 is shown in Figure 7-18 and described in Table 7-10.

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Figure 7-18 DEVICE_CTRL_2 Register

7	6	5	4	3	2	1	0
RESERVED			DIS_DSP	MUTE	RESERVED	CTRL_STATE
R/W			R/W	R/W	R/W	R/W

Table 7-10 DEVICE_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	000	This bit is reserved
4	DIS_DSP	R/W	1	DSP reset When the bit is made 0, DSP will start powering up and send out data. This needs to be made 0 only after all the input clocks are settled so that DMA channels do not go out of sync. 0: Normal operation 1: Reset the DSP
3	MUTE	R/W	0	Mute Both Left /Right Channel This bit issues soft mute request for the left/right channel. The volume will be smoothly ramped down/up to avoid pop/click noise. 0: Normal volume 1: Mute
2	RESERVED	R/W	0	This bit is reserved
1-0	CTRL_STATE	R/W	00	Device state control register 00: Deep Sleep 01: Sleep 10: Hi-Z, 11: PLAY

7.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]

I2C_PAGE_AUTO_INC is shown in Figure 7-19 and described in Table 7-11.

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Figure 7-19 I2C_PAGE_AUTO_INC Register

7	6	5	4	3	2	1	0
RESERVED				PAGE_AUTOINC_REG	RESERVED
R/W				R/W	R/W

Table 7-11 I2C_PAGE_AUTO_INC Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0000	This bit is reserved
3	PAGE_AUTOINC_REG	R/W	0	Page auto increment disable Disable page auto increment mode. for non -zero books. When end of page is reached it goes back to 8th address location of next page when this bit is 0. When this bit is 1 it goes to 0 th location of current page itself like in older part. 0: Enable Page auto increment 1: Disable Page auto increment
2-0	RESERVED	R/W	000	This bit is reserved

7.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]

SIG_CH_CTRL is shown in Figure 7-20 and described in Table 7-12.

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Figure 7-20 SIG_CH_CTRL Register

7	6	5	4	3	2	1	0
BCK_RATIO_CONFIGURE				FS_MODE
R/W				R/W

Table 7-12 SIG_CH_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	BCK_RATIO_CONFIGURE	R/W	0000	These bits indicate the configured BCK ratio, the number of BCK clocks in one audio frame. 0011: 32FS 0101: 64FS 0111: 128FS 1001: 256FS 1011: 512FS
3-0	FS_MODE	R/W	0000	FS Speed Mode These bits select the FS operation mode, which must be set according to the current audio sampling rate. 0000: Auto detection 0010: 8KHz 0100: 16KHz 0110: 32KHz 1000: 44.1KHz 1001: 48KHz 1010: 88.2KHz 1011: 96KHz Others Reserved

7.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]

CLOCK_DET_CTRL is shown in Figure 7-21 and described in Table 7-13.

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Figure 7-21 CLOCK_DET_CTRL Register

7	6	5	4	3	2	1	0
RESERVED	DIS_DET_PLL	DIS_DET_BCLK_RANGE	DIS_DET_FS	DIS_DET_BCLK	DIS_DET_MISS	RESERVED	RESERVED
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

Table 7-13 CLOCK_DET_CTRL Register Field Descriptions

Bit	Field	Type	Description
7	RESERVED	R/W	This bit is reserved
6	DIS_DET_PLL	R/W	Ignore PLL overate Detection This bit controls whether to ignore the PLL overrate detection. The PLL must be slow than 150MHz or an error will be reported. When ignored, a PLL overrate error will not cause a clock error. 0: Regard PLL overrate detection 1: Ignore PLL overrate detection
5	DIS_DET_BCLK_RANGE	R/W	Ignore BCK Range Detection This bit controls whether to ignore the BCK range detection. The BCK must be stable between 256KHz and 50MHz or an error will be reported. When ignored, a BCK range error will not cause a clock error. 0: Regard BCK Range detection 1: Ignore BCK Range detection
4	DIS_DET_FS	R/W	Ignore FS Error Detection This bit controls whether to ignore the FS Error detection. When ignored, FS error will not cause a clock error.But CLKDET_STATUS will report fs error. 0: Regard FS detection 1: Ignore FS detection
3	DIS_DET_BCLK	R/W	Ignore BCK Detection This bit controls whether to ignore the BCK detection against LRCK. The BCK must be stable between 32FS and 512FS inclusive or an error will be reported. When ignored, a BCK error will not cause a clock error. 0: Regard BCK detection 1: Ignore BCK detection
2	DIS_DET_MISS	R/W	Ignore BCK Missing Detection This bit controls whether to ignore the BCK missing detection. When ignored an BCK missing will not cause a clock error. 0: Regard BCK missing detection 1: Ignore BCK missing detection
1	RESERVED	R/W	This bit is reserved
0	RESERVED	R/W	This bit is reserved

7.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0h]

SDOUT_SEL is shown in Figure 7-22 and described in Table 7-14.

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Figure 7-22 SDOUT_SEL Register

7	6	5	4	3	2	1	0
RESERVED							SDOUT_SEL
							R/W

Table 7-14 SDOUT_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED		0	This bit is reserved
0	SDOUT_SEL	R	0	SDOUT Select. This bit selects what is being output as SDOUT pin. 0: SDOUT is the DSP output (post-processing) 1: SDOUT is the DSP input (pre-processing)

Bit

Field

Type

Reset

Description

7-1

RESERVED

This bit is reserved

SDOUT_SEL

SDOUT Select. This bit selects what is being output as SDOUT pin.

0: SDOUT is the DSP output (post-processing)

1: SDOUT is the DSP input (pre-processing)

7.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]

I2S_CTRL is shown in Figure 7-23 and described in Table 7-15.

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Figure 7-23 I2S_CTRL Register

7	6	5	4	3	2	1	0
RESERVED		BCK_INV	RESERVED		RESERVED		RESERVED
R/W		R/W	R/W	R	R		R/W

Table 7-15 I2S_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00	This bit is reserved
5	BCK_INV	R/W	0	BCK Polarity This bit sets the inverted BCK mode. In inverted BCK mode, the DAC assumes that the LRCK and DIN edges are aligned to the rising edge of the BCK. Normally they are assumed to be aligned to the falling edge of the BCK. 0: Normal BCK mode 1: Inverted BCK mode
4-0	RESERVED	R/W	00000	This bit is reserved

7.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]

SAP_CTRL1 is shown in Figure 7-24 and described in Table 7-16.

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Figure 7-24 SAP_CTRL1 Register

7	6	5	4	3	2	1	0
I2S_SHIFT_MSB	RESERVED	DATA_FORMAT		I2S_LRCLK_PULSE		WORD_LENGTH
R/W	R/W	R/W		R/W		R/W

Table 7-16 SAP_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	I2S_SHIFT_MSB	R/W	0	I2S Shift MSB
6	RESERVED	R/W	0	This bit is reserved
5-4	DATA_FORMAT	R/W	00	I2S Data Format These bits control both input and output audio interface formats for DAC operation. 00: I2S 01: TDM/DSP 10: RTJ 11: LTJ
3-2	I2S_LRCLK_PULSE	R/W	00	01: lrclk pulse < 8 SCLK. If the high width of LRCLK/FS in TDM/DSP mode is less than 8 cycles of SCK, these two bits need set to 01.
1-0	WORD_LENGTH	R/W	10	I2S Word Length These bits control both input and output audio interface sample word lengths for DAC operation. 00: 16 bits 01: 20 bits 10: 24 bits 11: 32 bits

7.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]

SAP_CTRL2 is shown in Figure 7-25 and described in Table 7-17.

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Figure 7-25 SAP_CTRL2 Register

7	6	5	4	3	2	1	0
I2S_SHIFT
R/W

Table 7-17 SAP_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	I2S_SHIFT	R/W	00000000	I2S Shift LSB These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of BCK from the starting (MSB) of audio frame to the starting of the desired audio sample. 000000000: offset = 0 BCK (no offset) 000000001: ofsset = 1 BCK 000000010: offset = 2 BCKs and 111111111: offset = 512 BCKs

7.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]

SAP_CTRL3 is shown in Figure 7-26 and described in Table 7-18.

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Figure 7-26 SAP_CTRL3 Register

7	6	5	4	3	2	1	0
RESERVED		LEFT_DAC_DPATH		RESERVED		RIGHT_DAC_DPATH
R/W		R/W		R/W		R/W

Table 7-18 SAP_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00	This bit is reserved
5-4	LEFT_DAC_DPATH	R/W	01	Left DAC Data Path. These bits control the left channel audio data path connection. 00: Zero data (mute) 01: Left channel data 10: Right channel data 11: Reserved (do not set)
3-2	RESERVED	R/W	00	This bit is reserved
1-0	RIGHT_DAC_DPATH	R/W	01	Right DAC Data Path. These bits control the right channel audio data path connection. 00: Zero data (mute) 01: Right channel data 10: Left channel data 11: Reserved (do not set)

7.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]

FS_MON is shown in Figure 7-27 and described in Table 7-19.

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Figure 7-27 FS_MON Register

7	6	5	4	3	2	1	0
RESERVED		BCLK_RATIO_HIGH		FS
R/W		R		R

Table 7-19 FS_MON Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00	This bit is reserved
5-4	BCLK_RATIO_HIGH	R	00	2 msbs of detected BCK ratio
3-0	FS	R	0000	These bits indicate the currently detected audio sampling rate. 0000: FS Error 0010: 8KHz 0100: 16KHz 0110: 32KHz 1000: Reserved 1001: 48KHz 1011: 96KHz Others Reserved

7.6.1.13 BCK_MON Register (Offset = 38h) [reset = 0x00]

BCK_MON is shown in Figure 7-28 and described in Table 7-20.

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Figure 7-28 BCK_MON Register

7	6	5	4	3	2	1	0
BCLK_RATIO_LOW
R

Table 7-20 BCK_MON Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	BCLK_RATIO_LOW	R	00000000	These bits indicate the currently detected BCK ratio, the number of BCK clocks in one audio frame. BCK = 32 FS~512 FS

Bit

Field

Type

Reset

Description

7-0

BCLK_RATIO_LOW

00000000

These bits indicate the currently detected BCK ratio, the number of BCK clocks in one audio frame.

BCK = 32 FS~512 FS

7.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]

CLKDET_STATUS is shown in Figure 7-29 and described in Table 7-21.

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Figure 7-29 CLKDET_STATUS Register

7	6	5	4	3	2	1	0
RESERVED		DET_STATUS
R/W		R

Table 7-21 CLKDET_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00	This bit is reserved
5	DET_STATUS	R	0	This bit indicates whether the BCLK is overrate or underrate
4	DET_STATUS	R	0	This bit indicates whether the PLL is overrate
3	DET_STATUS	R	0	This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled.
2	DET_STATUS	R	0	This bit indicates whether the BCK is missing or not.
1	DET_STATUS	R	0	This bit indicates whether the BCK is valid or not. The BCK ratio must be stable and in the range of 32-512FS to be valid.
0	DET_STATUS	R	0	In auto detection mode(reg_fsmode=0),this bit indicated whether the audio sampling rate is valid or not. In non auto detection mode(reg_fsmode!=0), Fs error indicates that configured fs is different with detected fs. Even FS Error Detection Ignore is set, this flag will be also asserted.

7.6.1.15 DIG_VOL_CTL Register (Offset = 4Ch) [reset = 30h]

DIG_VOL_CTL is shown in Figure 7-30 and described in Table 7-22.

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Figure 7-30 DIG_VOL_CTL Register

7	6	5	4	3	2	1	0
PGA
R/W

Table 7-22 DIG_VOL_CTR Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PGA	R/W	00110000	Digital Volume These bits control both left and right channel digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step. 00000000: +24.0 dB 00000001: +23.5 dB ........ and 00101111: +0.5 dB 00110000: 0.0 dB 00110001: -0.5 dB ....... 11111110: -103 dB 11111111: Mute

7.6.1.16 DIG_VOL_CTRL2 Register (Offset = 4Eh) [reset = 0x33]

DIG_VOL_CTRL2 is shown in Figure 7-31 and described in Table 7-23.

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Figure 7-31 DIG_VOL_CTRL2 Register

7	6	5	4	3	2	1	0
PGA_RAMP_DOWN_SPEED		PGA_RAMP_DOWN_STEP		PGA_RAMP_UP_SPEED		PGA_RAMP_UP_STEP
R/W		R/W		R/W		R/W

Table 7-23 DIG_VOL_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	PGA_RAMP_DOWN_SPEED	R/W	00	Digital Volume Normal Ramp Down Frequency These bits control the frequency of the digital volume updates when the volume is ramping down. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute)
5-4	PGA_RAMP_DOWN_STEP	R/W	11	Digital Volume Normal Ramp Down Step These bits control the step of the digital volume updates when the volume is ramping down. 00: Decrement by 4 dB for each update 01: Decrement by 2 dB for each update 10: Decrement by 1 dB for each update 11: Decrement by 0.5 dB for each update
3-2	PGA_RAMP_UP_SPEED	R/W	00	Digital Volume Normal Ramp Up Frequency These bits control the frequency of the digital volume updates when the volume is ramping up. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly restore the volume (Instant unmute)
1-0	PGA_RAMP_UP_STEP	R/W	11	Digital Volume Normal Ramp Up Step These bits control the step of the digital volume updates when the volume is ramping up. 00: Increment by 4 dB for each updat 01: Increment by 2 dB for each update 10: Increment by 1 dB for each update 11: Increment by 0.5 dB for each update

7.6.1.17 DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]

DIG_VOL_CTRL3 is shown in Figure 7-32 and described in Table 7-24.

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Figure 7-32 DIG_VOL_CTRL3 Register

7	6	5	4	3	2	1	0
FAST_RAMP_DOWN_SPEED		FAST_RAMP_DOWN_STEP		RESERVED
R/W		R/W		R/W

Table 7-24 DIG_VOL_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	FAST_RAMP_DOWN_SPEED	R/W	00	Digital Volume Emergency Ramp Down Frequency These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute)
5-4	FAST_RAMP_DOWN_STEP	R/W	11	Digital Volume Emergency Ramp Down Step These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute. 00: Decrement by 4 dB for each update 01: Decrement by 2 dB for each update 10: Decrement by 1 dB for each update 11: Decrement by 0.5 dB for each update
3-0	RESERVED	R/W	0000	This bit is reserved

7.6.1.18 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]

AUTO_MUTE_CTRL is shown in Figure 7-33 and described in Table 7-25.

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Figure 7-33 AUTO_MUTE_CTRL Register

7	6	5	4	3	2	1	0
RESERVED					REG_AUTO_MUTE_CTRL
R/W					R/W

Table 7-25 AUTO_MUTE_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	00000	This bit is reserved
2	REG_AUTO_MUTE_CTRL	R/W	1	0: Auto mute left channel and right channel independently. 1: Auto mute left and right channels only when both channels are about to be auto muted
1	REG_AUTO_MUTE_CTRL	R/W	1	0: Disable right channel auto mute 1: Enable right channel auto mute
0	REG_AUTO_MUTE_CTRL	R/W	1	0: Disable left channel auto mute 1: Enable left channel auto mute bit2: .

7.6.1.19 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]

AUTO_MUTE_TIME is shown in Figure 7-34 and described in Table 7-26.

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Figure 7-34 AUTO_MUTE_TIME Register

7	6	5	4	3	2	1	0
RESERVED	AUTOMUTE_TIME_LEFT			RESERVED	AUTOMUTE_TIME_RIGHT
R/W	R/W			R/W	R/W

Table 7-26 AUTO_MUTE_TIME Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0	This bit is reserved
6-4	AUTOMUTE_TIME_LEFT	R/W	000	Auto Mute Time for Left Channel These bits specify the length of consecutive zero samples at left channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec
3	RESERVED	R/W	0	This bit is reserved
2-0	AUTOMUTE_TIME_RIGHT	R/W	000	Auto Mute Time for Right Channel These bits specify the length of consecutive zero samples at right channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec

7.6.1.20 ANA_CTRL Register (Offset = 53h) [reset = 0x00]

ANA_CTRL is shown in Figure 7-35 and described in Table 7-27.

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Figure 7-35 ANA_CTRL Register

7	6	5	4	3	2	1	0
ANA_CTRL
R/W

Table 7-27 ANA_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

R/W

This bit is reserved

6-5

ANA_CTRL

R/W

Class-D bandwidth control.

00: 80kHz;

01: 100kHz;

10: 120kHz;

11: 175kHz.

With Fsw=768kHz, 175kHz bandwidth should be selected for high audio performance.

4-0

RESERVED

R/W

00000

These bits are reserved

7.6.1.21 AGAIN Register (Offset = 54h) [reset = 0x00]

AGAIN is shown in Figure 7-36 and described in Table 7-28.

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Figure 7-36 AGAIN Register

7	6	5	4	3	2	1	0
RESERVED			ANA_GAIN
R/W			R/W

Table 7-28 AGAIN Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	000	This bit is reserved
4-0	ANA_GAIN	R/W	00000	Analog Gain Control , with 0.5dB one step This bit controls the analog gain. 00000: 0 dB (29.5V peak voltage) 00001: -0.5db 11111: -15.5 dB

7.6.1.22 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]

BQ_WR_CTRL1 is shown in Figure 7-37 and described in Table 7-29.

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Figure 7-37 BQ_WR_CTRL1 Register

7	6	5	4	3	2	1	0
RESERVED							BQ_WR_FIRST_COEF
R/W							R/W

Table 7-29 BQ_WR_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	0000000	This bit is reserved
0	BQ_WR_FIRST_COEF	R/W	0	Indicate the first coefficient of a BQ is starting to write.

7.6.1.23 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]

DAC_CTRL is shown in Figure 7-38 and described in Table 7-30.

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Figure 7-38 DAC_CTRL Register

7	6	5	4	3	2	1	0
DAC_FREQUENCY_SEL	DAC_DITHER_EN		DAC_DITHER			DAC_CTRL_DEM_SEL
R/W	R/W		R/W			R/W

Table 7-30 DAC_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DAC_FREQUENCY_SEL	R/W	1	DAC Frequency Select 0: 6.144MHz 1: 3.072MHz
6-5	DAC_DITHER_EN	R/W	11	DITHER_EN, 00: disable both stage dither 01: enable main stage dither 10: enable second stage dither 11: enbale both stage dither
4-2	DAC_DITHER	R/W	110	Dither level 100: -2^-7 101: -2^-8 110: -2^-9 111: -2^-10 000: -2^-13 001: -2^-14 010: -2^-15 011: -2^-16
1-0	DAC_CTRL_DEM_SEL	R/W	00	00: Enable DEM 11: Disable DEM

7.6.1.24 ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]

ADR_PIN_CTRL is shown in Figure 7-39 and described in Table 7-31.

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Figure 7-39 ADR_PIN_CTRL Register

7	6	5	4	3	2	1	0
RESERVED							ADR_OE
							R/W - 0x0

Table 7-31 ADR_PIN_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

0000000

This bit is reserved

ADR_OE

R/W

ADR Output Enable This bit sets the direction of the ADR pin

0: ADR is input

1: ADR is output

7.6.1.25 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]

ADR_PIN_CONFIG is shown in Figure 7-40 and described in Table 7-32.

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Figure 7-40 ADR_PIN_CONFIG Register

7	6	5	4	3	2	1	0
RESERVED			ADR_PIN_CONFIG
			R/W

Table 7-32 ADR_PIN_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

RESERVED

R/W

000

These bits are reserved

4-0

ADR_PIN_CONFIG

R/W

00000

00000: off (low)

00011: Auto mute flag (asserted when both L and R channels are auto muted)

00100: Auto mute flag for left channel 0101: Auto mute flag for right channel

00110: Clock invalid flag (clock error or clock missing)

00111: Reserved

01001: Reserved

01011: ADR as FAULTZ output

7.6.1.26 DSP_MISC Register (Offset = 66h) [reset = 0h]

DSP_MISC is shown in Figure 7-41 and described in Table 7-33.

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Figure 7-41 DSP_MISC Register

7	6	5	4	3	2	1	0
BYPASS_CONTROL
R/W

Table 7-33 DSP_MISC Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0000	These bits are reserved
3	BYPASS CONTROL	R/W	0	1: Left and Right will have use unique coef 0->Right channel will share left channel coefficient
2	BYPASS CONTROL	R/W	0	1: bypass 128 tap FIR
1	BYPASS CONTROL	R/W	0	1: bypass DRC (Only bypass DRC in L/R channel)
0	BYPASS CONTROL	R/W	0	1: bypass EQ (Only bypass EQs in L/R channel)

7.6.1.27 DIE_ID Register (Offset = 67h) [reset = 0h]

DIE_ID is shown in Figure 7-42 and described in Table 7-34.

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Figure 7-42 DIE_ID Register

7	6	5	4	3	2	1	0
DIE_ID
R-0h

Table 7-34 DIE_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIE_ID	R	0h	DIE ID

7.6.1.28 POWER_STATE Register (Offset = 68h) [reset = 0x00]

POWER_STATE is shown in Figure 7-43 and described in Table 7-35.

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Figure 7-43 POWER_STATE Register

7	6	5	4	3	2	1	0
STATE_RPT
R

Table 7-35 POWER_STATE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

STATE_RPT

00000000

0: Deep sleep

1: Sleep

2: HIZ

3: Play

Others: reserved

7.6.1.29 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]

AUTOMUTE_STATE is shown in Figure 7-44 and described in Table 7-36.

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Figure 7-44 AUTOMUTE_STATE Register

7	6	5	4	3	2	1	0
RESERVED						ZERO_RIGHT_MON	ZERO_LEFT_MON
R						R	R

Table 7-36 AUTOMUTE_STATE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

RESERVED

000000

This bit is reserved

ZERO_RIGHT_MON

This bit indicates the auto mute status for right channel.

0: Not auto muted

1: Auto muted

ZERO_LEFT_MON

This bit indicates the auto mute status for left channel.

0: Not auto muted

1: Auto muted

7.6.1.30 PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]

PHASE_CTRL is shown in Figure 7-45 and described in Table 7-37.

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Figure 7-45 PHASE_CTR Register

7	6	5	4	3	2	1	0
RESERVED				RAMP_PHASE_SEL		PHASE_SYNC _SEL	PHASE_SYNC _EN
R/W				R/W		R/W	R/W

Table 7-37 PHASE_CTR Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0000	This bit is reserved
3-2	RAMP_PHASE_SEL	R/W	00	Select ramp clock phase when multi devices integrated in one system to reduce EMI and peak supply peak current, it is recomended set all devices the same RAMP frequency and same spread spectrum. it must be set before driving device into PLAY mode if this feature is needed. 00: phase 0 01: phase1 10: phase2 11: phase3
1	I2S_SYNC_EN	R/W	0	Use I2S to synchronize output PWM phase 0: Disable 1: Enable
0	PHASE_SYNC_EN	R/W	0	0: RAMP phase sync disable 1: RAMP phase sync enable

7.6.1.31 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]

SS_CTRL0 is shown in Figure 7-46 and described in Table 7-38.

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Figure 7-46 SS_CTRL0 Register

7	6	5	4	3	2	1	0
RESERVED	RESERVED	SS_PRE_DIV_SEL	SS_MANUAL_MODE	RESERVED		SS_RDM_EN	SS_TRI_EN
R/W	R/W	R/W	R/W	R/W		R/W	R/W

Table 7-38 SS_CTRL0 Register Field Descriptions

Bit	Field	Type	Description
7	RESERVED	R/W	This bit is reserved
6	RESERVED	R/W	This bit is reserved
5	SS_PRE_DIV_SEL	R/W	Select pll clock divide 2 as source clock in manual mode
4	SS_MANUAL_MODE	R/W	Set ramp ss controller to manual mode
3-2	RESERVED	R/W	This bit is reserved
1	SS_RDM_EN	R/W	Random SS enable
0	SS_TRI_EN	R/W	Triangle SS enable

7.6.1.32 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]

SS_CTRL1 is shown in Figure 7-47 and described in Table 7-39.

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Figure 7-47 SS_CTRL1 Register

7	6	5	4	3	2	1	0
RESERVED	SS_RDM_CTRL			SS_TRI_CTRL
R/W	R/W			R/W

Table 7-39 SS_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0	This bit is reserved
6-4	SS_RDM_CTRL	R/W	000	Random SS range control
3-0	SS_TRI_CTRL	R/W	0000	Triangle SS frequency and range control

7.6.1.33 SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]

SS_CTRL2 is shown in Figure 7-48 and described in Table 7-40.

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Figure 7-48 SS_CTRL2 Register

7	6	5	4	3	2	1	0
TM_FREQ_CTRL
R/W

Table 7-40 SS_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	TM_FREQ_CTRL	R/W	01010000	Control ramp frequency in manual mode, F=61440000/N

7.6.1.34 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]

SS_CTRL3 is shown in Figure 7-49 and described in Table 7-41.

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Figure 7-49 SS_CTRL3 Register

7	6	5	4	3	2	1	0
TM_DSTEP_CTRL				TM_USTEP_CTRL
R/W				R/W

Table 7-41 SS_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	SS_TM_DSTEP_CTRL	R/W	0001	Control triangle mode spread spectrum fall step in ramp ss manual mode
3-0	SS_TM_USTEP_CTRL	R/W	0001	Control triangle mode spread spectrum rise step in ramp ss manual mode

7.6.1.35 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]

SS_CTRL4 is shown in Figure 7-50 and described in Table 7-42.

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Figure 7-50 SS_CTRL4 Register

7	6	5	4	3	2	1	0
RESERVED	TM_AMP_CTRL		SS_TM_PERIOD_BOUNDRY
R/W	R/W		R/W

Table 7-42 SS_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0	This bit is reserved
6-5	TM_AMP_CTRL	R/W	01	Control ramp amp ctrl in ramp ss manual model
4-0	SS_TM_PERIOD_BOUNDRY	R/W	00100	Control triangle mode spread spectrum boundary in ramp ss manual mode

7.6.1.36 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]

CHAN_FAULT is shown in Figure 7-51 and described in Table 7-43.

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Figure 7-51 CHAN_FAULT Register

7	6	5	4	3	2	1	0
RESERVED				CH1_DC_1	CH2_DC_1	CH1_OC_I	CH2_OC_I
R				R	R	R	R

Table 7-43 CHAN_FAULT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0000	This bit is reserved
3	CH1_DC_1	R	0	Left channel DC fault
2	CH2_DC_1	R	0	Right channel DC fault
1	CH1_OC_I	R	0	Left channel over current fault
0	CH2_OC_I	R	0	Right channel over current fault

7.6.1.37 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]

GLOBAL_FAULT1 is shown in Figure 7-52 and described in Table 7-44.

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Figure 7-52 GLOBAL_FAULT1 Register

7	6	5	4	3	2	1	0
OTP_CRC_ERROR	BQ_WR_ERROR				CLK_FAULT_I	PVDD_OV_I	PVDD_UV_I
R	R				R	R	R

Table 7-44 GLOBAL_FAULT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OTP_CRC_ERROR	R	0h	Indicate OTP CRC check error.
6	BQ_WR_ERROR	R	0h	The recent BQ is written failed
5-3	RESERVED	R	0h	This bit is reserved
2	CLK_FAULT_I	R	0h	Clock fault
1	PVDD_OV_I	R	0h	PVDD OV fault
0	PVDD_UV_I	R	0h	PVDD UV fault

7.6.1.38 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]

GLOBAL_FAULT2 is shown in Figure 7-53 and described in Table 7-45.

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Figure 7-53 GLOBAL_FAULT2 Register

7	6	5	4	3	2	1	0
RESERVED					RESERVED		OTSD_I
R					R		R

Table 7-45 GLOBAL_FAULT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R	0000000	This bit is reserved
0	OTSD_I	R	0	Over temperature shut down fault

7.6.1.39 OT WARNING Register (Offset = 73h) [reset = 0x00]

OT_WARNING is shown in Figure 7-54 and described in Table 7-46.

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Figure 7-54 OT_WARNING Register

7	6	5	4	3	2	1	0
RESERVED		RESERVED			OTW	RESERVED
R		R		R	R	R	R

Table 7-46 OT_WARNING Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	00	This bit is reserved
5-3	RESERVED	R	000	This bit is reserved
2	OTW	R	0	Over temperature warning ,135C
1-0	RESERVED	R	00	This bit is reserved

7.6.1.40 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]

PIN_CONTROL1 is shown in Figure 7-55 and described in Table 7-47.

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Figure 7-55 PIN_CONTROL1 Register

7	6	5	4	3	2	1	0
MASK_OTSD	MASK_DVDD_UV	MASK_DVDD_OV	MASK_CLK_FAULT	MASK_PVDD_UV	MASK_PVDD_OV	MASK_DC	MASK_OC
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

Table 7-47 PIN_CONTROL1 Register Field Descriptions

Bit	Field	Type	Description
7	MASK_OTSD	R/W	Mask OTSD fault report
6	MASK_DVDD_UV	R/W	Mask DVDD UV fault report
5	MASK_DVDD_OV	R/W	Mask DVDD OV fault report
4	MASK_CLK_FAULT	R/W	Mask clock fault report
3	MASK_PVDD_UV	R/W	Mask PVDD UV fault report
2	MASK_PVDD_OV	R/W	Mask PVDD OV fault report
1	MASK_DC	R/W	Mask DC fault report
0	MASK_OC	R/W	Mask OC fault report

7.6.1.41 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]

PIN_CONTROL2 is shown in Figure 7-56 and described in Table 7-48.

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Figure 7-56 PIN_CONTROL2 Register

7	6	5	4	3	2	1	0
RESERVED		CLKFLT_LATCH_EN	OTSD_LATCH_EN	OTW_LATCH_EN	MASK_OTW	RESERVED
		R/W	R/W	R/W	R/W

Table 7-48 PIN_CONTROL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	11	This bit is reserved
5	CLKFLT_LATCH_EN	R/W	1	Enable clock fault latch
4	OTSD_LATCH_EN	R/W	1	Enable OTSD fault latch
3	OTW_LATCH_EN	R/W	1	Enable OT warning latch
2	MASK_OTW	R/W	0	Mask OT warning report
1-0	RESERVED	R/W	00	This bit is reserved

7.6.1.42 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]

MISC_CONTROL is shown in Figure 7-57 and described in Table 7-49.

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Figure 7-57 MISC_CONTROL Register

7	6	5	4	3	2	1	0
DET_STATUS_LATCH	RESERVED		OTSD_AUTO_REC_EN	RESERVED
R/W	R/W		R/W	R/W

Table 7-49 MISC_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DET_STATUS_LATCH	R/W	0	1:Latch clock detection status 0:Don't latch clock detection status
6-5	RESERVED	R/W	00	This bit is reserved
4	OTSD_AUTO_REC_EN	R/W	0	OTSD auto recovery enable
3-0	RESERVED	R/W	0000	This bit is reserved

7.6.1.43 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]

FAULT_CLEAR is shown in Figure 7-58 and described in Table 7-50.

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Figure 7-58 FAULT_CLEAR Register

7	6	5	4	3	2	1	0
ANALOG_FAULT_CLEAR	RESERVED
W	R/W

Table 7-50 FAULT_CLEAR Register Field Descriptions

Bit

Field

Type

Reset

Description

ANALOG_FAULT_CLEAR

WRITE CLEAR BIT.

Once write this bit to 1, device will clear analog fault

6-0

RESERVED

R/W

0000000

This bit is reserved