The TAS5805M devices have flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio Interface.

Figure 7-1 Audio Flow with Respective Clocks

Figure 7-1 shows the basic data flow and clock distribution.

The Serial Audio Interface typically has 3 connection pins which are listed as follows:

• SCLK (Bit Clock)
• LRCLK/FS (Left Right Word Clock and Frame Sync)
• SDIN (Input Data)

The device has an internal PLL that is used to take SCLK (Bit Clock) as reference clock and create the higher rate clocks required by the DSP and the DAC clock.

The TAS5805M device has an audio sampling rate detection circuit that automatically senses the sampling frequency. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz – 96 kHz are supported. The sampling frequency detector sets the clock for DAC and DSP automatically.