The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and TDM/DSP data. Data formats are selected via Register (Register Address 0x33h -D[5:4]). If the high width of LRCLK/FS in TDM/DSP mode is less than 8 cycles of SCK, the register (Register Address 0x33h -D[3:2]) should set to 01. All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. All the data formats, word length and clock rate supported by this device are shown in Table 1. The data formats are detailed in Figure 8-2 through Figure 8-6. The word length are selected via Register (Register Address 0x33h -D[1:0]). The offsets of data are selected via Register (Register Address 0x33h -D[7]) and Register (Register Address 0x34h -D[7:0]). Default setting is I2S and 24 bit word length.

Figure 8-2 Left Justified Audio Data Format

I²S Data Format; L-channel = LOW, R-channel = HIGH

Figure 8-3 I²S Audio Data Format

Right Justified Data Format; L-channel = HIGH, R-channel = LOW

Figure 8-4 Right Justified Audio Data Format

TDM Data Format with OFFSET = 0

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 8-5 TDM 1 Audio Data Format

TDM Data Format with OFFSET = 1

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 8-6 TDM 2 Audio Data Format