10.3.1.1 I²S Mode

I²S timing uses the FSYNC pin to define when the data being transmitted is for the left channel and when the data is for the right channel. The FSYNC pin is low for the left channel and high for the right channel. The bit clock, SCLK, runs at 32 × f_S or 64 × f_S and is used to clock in the data. A delay of one bit clock occurs from the time the FSYNC signal changes state to the first bit of data on the data lines. The data is presented in 2s-complement form (MSB-first). The data is valid on the rising edge of the bit clock and is used to clock in the data.

10.3.1.2 Left-Justified Timing

Left-justified (LJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left channel and when the data is for the right channel. The FSYNC pin is high for the left channel and low for the right channel. A bit clock running at 32 × f_S or 64 × f_S is used to clock in the data. The first bit of data appears on the data lines at the same time FSYNC toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. Digital words can be 16-bits or 24-bits wide and pad any unused trailing data-bit positions in the left-right (L/R) frame with zeros.

10.3.1.3 Right-Justified Timing

Right-justified (RJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left channel and when the data is for the right channel. The FSYNC pin is high for the left channel and low for the right channel. A bit clock running at 32 × f_S or 64 × f_S is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for 24-bit data) after the FSYNC pin toggles. In RJ mode the LSB of data is always clocked by the last bit clock before the FSYNC pin transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The device pads the unused leading data-bit positions in the L/R frame with zeros.

10.3.1.4 TDM Mode

TDM mode supports 4 or 8 channels of audio data. The TDM mode is automatically selected when the TDM clocks are present. The device can be configured through I²C to use different stereo pairs in the TDM data stream. The TDM mode supports 16-bit, 24-bit, and 32-bit input data lengths.

In TDM mode, the SCLK pin must be 128 or 256, depending on the TDM slot size. In TDM mode SCLK and MCLK can be connected together. If SCLK and MCLK are connected together than FSYNC should be minimum 2 MCLK pulses long.

In TDM mode, the SDIN1 pin (pin 15) is used for digital audio data. TI recommends to connect the unused SDIN2 pin (pin 16) to ground. Table 1 lists register settings for the TDM channel selection.

If PBTL mode is programmed for channel 1/2 the datasource can be set according to Table 2.

10.3.1.5 Supported Clock Rates

The device supports MCLK rates of 128 × f_S, 256 × f_S, or 512 × f_S.

The device supports SCLK rates of 32 × f_Sor 64 × f_S in I²S, LJ or RJ modes or 128 × f_S, or 256 × f_S in TDM mode.

The device supports FSYNC rates of 44.1 kHz, 48 kHz, or 96 kHz.

The maximum clock frequency is 25 MHz. Therefore, for a 96 kHz FSYNC rate, the maximum MCLK rate is
256 × f_S.

The MCLK clock must not be in phase to sync to SCLK. Duty cycle of 50% is required for 128x FSYNC, for 256x and 512x 50% duty is not required.

10.3.1.6 Audio-Clock Error Handling

When any kind of clock error, MCLK-FSYNC or SCLK-FSYNC ratio, or clock halt is detected, the device puts all channels into the Hi-Z state. When all audio clocks are within the expected range, the device automatically returns to the state it was in. See the Timing Requirements table for timing requirements.

Table 3. Output Switch Frequency Option

10.3.7.1 DC Load Diagnostics

The DC load diagnostics are used to verify the load connected. The DC diagnostics consists of four tests: short-to-power (S2P), short-to-ground (S2G), open-load (OL), and shorted-load (SL). The S2P and S2G tests trigger if the impedance to GND or a power rail is below that specified in the Specifications section. The diagnostic detects a short to vehicle battery even when the supply is boosted. The SL test has an I²C-configurable threshold depending on the expected load to be connected. Because the speakers connected to each channel might be different, each channel can be assigned a unique threshold value. The OL test reports if the select channel has a load impedance greater than the limits in the Specifications section.

Figure 39. DC Load Diagnostic Reporting Thresholds

10.3.7.2 Line Output Diagnostics

The device also includes an optional test to detect a line-output load. A line-output load is a high-impedance load that is above the open-load (OL) threshold such that the DC-load diagnostics report an OL condition. After an OL condition is detected on a channel, if the line output detection bit is also set, the channel checks if a line-output load is present as well. This test is not pop free, so if an external amplifier is connected it should be muted.

10.3.7.3 AC Load Diagnostics

The AC load diagnostic is used to determine the proper connection of a capacitively coupled speaker or tweeter when used with a passive crossover. The AC load diagnostic is controlled through I²C. The AC diagnostics requires an external input signal and reports the approximate load impedance and phase. The selected signal frequency should create current flow through the desired speaker for proper detection. If multiple channels must be tested, the diagnostics should be run in series. The AC load-diagnostic test procedure is as follows.

For load-impedance detection, use the following test procedure:

1. Set the channels to be tested into the Hi-Z state.
2. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0.
3. Apply a full-scale input signal from the DSP for the tested channels with the desired frequency (recommended 10 kHz to 20 kHz).

NOTE

The device ramps the signal up and down automatically to prevent pops and clicks.

4. Set the device into the AC diagnostic mode (set bits 3:0 in register 0x15 to 1 for CH1 and CH2, set bit 3 in register 0x15 to 1, and set bit 1 in register 0x15 to 1 for PBTL12).
5. Read back the AC impedance (register 0x17 through register 0x1A).

When the test is complete the channel reporting register indicates the status change from the AC diagnostic mode to the Hi-Z state. The detected impedance is stored in the appropriate I²C register.

For loopback delay detection, use the following test procedure for either BTL mode or PBTL mode:

• BTL mode
  1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.
  2. Apply a 0-dBFS 19K signal and enable AC load diagnostics. CH1 and CH2 reuse the AC sensing loop of CH1 (set bit 3 in register 0x15 to 1).
  3. Read back the AC_LDG_PHASE1 value (register 0x1B and register 0x1C).

  When the test is complete, the channel reporting register indicates the status change from the AC diagnostic mode to the Hi-Z state. The detected impedance is stored in the appropriate I²C register.

• PBTL mode
  1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.
  2. Set the PBTL CH12 bits (see register 0x00) to 0 without toggling SDz pin to enter BTL mode only for load diagnostics.
  3. Apply a 0 dBFS 19K signal and enable AC load diagnostics. For PBTL_12, enable the AC sensing loop of CH1 (set bit 3 in register 0x15 to 1).
  4. Read back the AC_LDG_PHASE1 (register 0x1B and register 0x1C).
  5. Set the PBTL CH12 bits (see register 0x00) to 1 to go back to PBTL mode for load diagnostics.

10.3.8.1 Overcurrent Limit (I_LIMIT)

The overcurrent limit terminates each PWM pulse to limit the output current flow when the current limit (I_LIMIT) is exceeded. Power is limited but operation continues without disruption and prevents undesired shutdown for transient music events. I_LIMIT is not reported as a fault condition to either registers or the FAULT pin. Each channel is independently monitored and limited. The two programable levels can be set by bit 4 in the miscellaneous control 1 register (address 0x01).

10.3.8.2 Overcurrent Shutdown (I_SD)

If the output load current reaches I_SD, such as an output short to GND, then a peak current limit occurs which shuts down the channel. The time to shutdown the channel varies depending on the severity of the short condition. The affected channel is placed into the Hi-Z state, the fault is reported to the register, and the FAULT pin is asserted. If the diagnostics are enabled then the device automatically starts diagnostics on the channel and, if no load failure is found, the device restarts. If a load fault is found the device continues to rerun the diagnostics once per second. Because this hiccup mode is using the diagnostics, no high current is created. If the diagnostics are disabled the device sets the state for that channel to Hi-Z and requires the MCU to take the appropriate action.

Two programable levels can be set by bit 4 in the miscellaneous control 1 register (address 0x01).

10.3.8.3 DC Detect

This circuit detects a DC offset continuously during normal operation at the output of the amplifier. If the DC offset exceeds the threshold, that channel is placed in the Hi-Z state, the fault is reported to the I²C register, and the FAULT pin is asserted. A register bit can be used to mask reporting to the FAULT pin if required.

10.3.8.4 Clip Detect

The clip detect is reported on the WARN pin if 100% duty-cycle PWM if reached for a minimum of 20 cycles. If any channel is clipping, the clipping is reported to the pin. The clip detect is latched and can be cleared by I²C . Masking the clip reporting to the pin is possible through I²C.

10.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)

Four overtemperature warning levels are available in the device that can be selected (see the Register Maps section for thresholds). When the junction temperature exceeds the warning level, the WARN pin is asserted unless the mask bit has been set to disable reporting. The device functions until the OTSD value is reached at which point all channels are placed in the Hi-Z state and the FAULT pin is asserted. When the junction temperature returns to normal levels, the device automatically recovers and places all channels into the state indicated by the register settings.

10.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]

In addition to the global OTW, each channel also has an individual overtemperature warning and shutdown. If a channel exceeds the OTW(i) threshold, the warning register bit is set as the WARN pin is asserted unless the mask bit has been set to disable reporting. If the channel temperature exceeds the OTSD(i) threshold then that channel goes to the Hi-Z state until the temperature drops below the OTW(i) threshold at which point the channel goes to the state indicated by the state control register.

10.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)

The undervoltage (UV) protection detects low voltages on the PVDD and VBAT pins. In the event of an UV condition, the FAULT pin is asserted and the I²C register is updated. A power-on reset (POR) on the VDD pin causes the I²C to goes to the high-impedance (Hi-Z) state and all registers are reset to default values. At power-on or after a POR event, the POR warning bit and WARN pin are asserted.

10.3.8.8 Overvoltage (OV) and Load Dump

The overvoltage (OV) protection detects high voltages on the PVDD pin. If the PVDD pin reaches the OV threshold, the FAULT pin is asserted and the I²C register is updated. The device can withstand 40 V load-dump voltage spikes.

10.3.9.1 Vehicle-Battery Power-Supply Sequence

The device can accept any sequence of the VBAT, PVDD and VDD supply.

In a typical system, the VBAT and PVDD supplies are both connected to the vehicle battery and power up at the same time. The VDD supply should be applied after the VBAT and PVDD supplies are within the recommended operating range. When removing power from the device, TI recommends to deassert the VDD supply first then the VBAT, PVDD, or both supplies which provides the lowest click and pop performance.

10.3.9.2 Boosted Power-Supply Sequence

In this case, the VBAT and PVDD inputs are not connected to the same supply.

When powering up, apply the VBAT supply first, the VDD supply second, and the PVDD supply last.

When powering down, remove the PVDD supply first, the VDD supply second, and the VBAT supply last.

10.3.10.1 FAULT

The FAULT pin reports faults and is active low under any of the following conditions:

• Any channel faults (overcurrent or DC detection)
• Overtemperature shutdown
• Overvoltage or undervoltage conditions on the VBAT or PVDD pins
• Clock errors

The FAULT pin is deactivated when none of the previously listed conditions exist.

Register bits are available to mask fault categories from reporting to the FAULT pin. These bits only mask the setting of the pin and do not affect the register reporting or protection of the device. By default all faults are reported to the pin. See the Register Maps section for a description of the mask settings.

This pin is an open-drain output with an internal 100 kΩ pullup resistor to VDD.

10.3.10.2 WARN

This active-low output pin reports audio clipping, overtemperature warnings, and POR events.

Clipping is reported if any channel is at the maximum modulation for 20 consecutive PWM clocks which results in a 10-µs delay to report the onset of clipping. The warning bit is sticky and can be cleared by the CLEAR FAULT bit (bit 7) in register 0x21.

An overtemperature warning (OTW) is reported if the general temperature or any of the channel temperature warnings are set. The warning temperature can be set through bits 5 and 6 in register 0x01.

Register bits are available to mask either clipping or OTW reporting to the pin. These bits only mask the setting of the pin and do not affect the register reporting. By default both clipping and OTW are reported.

The WARN pin is latched and can be cleared by writing the CLEAR FAULT bit (bit 7) in register 0x21.

This pin is an open-drain output with an internal 100 kΩ pullup resistor to VDD.

10.3.10.3 MUTE

This active-low input pin is used for hardware control of the mute and unmute function for all channels.

This pin has a 100 kΩ internal pulldown resistor.

10.3.10.4 STANDBY

When this active-low input pin is asserted, the device goes into shutdown and current draw is limited. This pin can be used to shut down the device rapidly. The outputs are ramped down in less than 5 ms if the device is not already in the Hi-Z state. The I²C bus goes into the high-impedance (Hi-Z) state when in STANDBY.

This pin has a 100 kΩ internal pulldown resistor.

Table 5. Operating Modes

Table 6. Global Faults and Actions

Table 7. Channel Faults and Actions

Table 8. I²C Addresses

Table 10. Mode Control Field Descriptions

Table 11. Misc Control 1 Field Descriptions

Table 12. Misc Control 2 Field Descriptions

Table 13. SAP Control Field Descriptions

Table 14. Channel State Control Field Descriptions

Table 15. Ch x Volume Control Field Descriptions

Table 16. DC Load Diagnostics Control 1 Field Descriptions

Table 17. DC Load Diagnostics Control 2 Field Descriptions

Table 18. DC Load Diagnostics Report 1 Field Descriptions

Table 19. DC Load Diagnostics Report 3 Line Output Field Descriptions

Table 20. State-Reporting Field Descriptions

Table 21. Channel Faults Field Descriptions

Table 22. Global Faults 1 Field Descriptions

Table 23. Global Faults 2 Field Descriptions

Table 24. Warnings Field Descriptions

Table 25. Pin Control Field Descriptions

Table 26. AC Load Diagnostic Control 1 Field Descriptions

Table 27. AC Load Diagnostic Control 2 Field Descriptions

Table 28. Chx AC LDG Impedance Report Field Descriptions

Table 29. AC LDG Phase High Report Field Descriptions

Table 30. AC LDG Phase Low Report Field Descriptions

Table 31. AC LDG STI High Report Field Descriptions

Table 32. Chx AC LDG STI Low Report Field Descriptions

Table 33. Misc Control 3 Field Descriptions

Table 34. Clip Control Field Descriptions

Table 35. Clip Window Field Descriptions

Table 36. Clip Warning Field Descriptions

Table 37. ILIMIT Status Field Descriptions

Table 38. Misc Control 4 Field Descriptions