ZHCSJB8 February   2019 TAS6424M-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     PCB 区域
  4. 4 修订历史记录
  5. 5 说明（续）
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Serial Audio Port
        1. 10.3.1.1 I2S Mode
        2. 10.3.1.2 Left-Justified Timing
        3. 10.3.1.3 Right-Justified Timing
        4. 10.3.1.4 TDM Mode
        5. 10.3.1.5 Supported Clock Rates
        6. 10.3.1.6 Audio-Clock Error Handling
      2. 10.3.2  High-Pass Filter
      3. 10.3.3  Volume Control and Gain
      4. 10.3.4  High-Frequency Pulse-Width Modulator (PWM)
      5. 10.3.5  Gate Drive
      6. 10.3.6  Power FETs
      7. 10.3.7  Load Diagnostics
        1. 10.3.7.1 DC Load Diagnostics
        2. 10.3.7.2 Line Output Diagnostics
        3. 10.3.7.3 AC Load Diagnostics
          1. 10.3.7.3.1 Impedance Magnitude Measurement
          2. 10.3.7.3.2 Impedance Phase Reference Measurement
          3. 10.3.7.3.3 Impedance Phase Measurement
      8. 10.3.8  Protection and Monitoring
        1. 10.3.8.1 Overcurrent Limit (ILIMIT)
        2. 10.3.8.2 Overcurrent Shutdown (ISD)
        3. 10.3.8.3 DC Detect
        4. 10.3.8.4 Clip Detect
        5. 10.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. 10.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. 10.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)
        8. 10.3.8.8 Overvoltage (OV) and Load Dump
      9. 10.3.9  Power Supply
        1. 10.3.9.1 Vehicle-Battery Power-Supply Sequence
        2. 10.3.9.2 Boosted Power-Supply Sequence
      10. 10.3.10 Hardware Control Pins
        1. 10.3.10.1 FAULT
        2. 10.3.10.2 WARN
        3. 10.3.10.3 MUTE
        4. 10.3.10.4 STANDBY
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operating Modes and Faults
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Communication Bus
      2. 10.5.2 I2C Bus Protocol
      3. 10.5.3 Random Write
      4. 10.5.4 Sequential Write
      5. 10.5.5 Random Read
      6. 10.5.6 Sequential Read
    6. 10.6 Register Maps
      1. 10.6.1  Mode Control Register (address = 0x00) [default = 0x00]
        1. Table 10. Mode Control Field Descriptions
      2. 10.6.2  Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
        1. Table 11. Misc Control 1 Field Descriptions
      3. 10.6.3  Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
        1. Table 12. Misc Control 2 Field Descriptions
      4. 10.6.4  SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
        1. Table 13. SAP Control Field Descriptions
      5. 10.6.5  Channel State Control Register (address = 0x04) [default = 0x55]
        1. Table 14. Channel State Control Field Descriptions
      6. 10.6.6  Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]
        1. Table 15. Ch x Volume Control Field Descriptions
      7. 10.6.7  DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
        1. Table 16. DC Load Diagnostics Control 1 Field Descriptions
      8. 10.6.8  DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
        1. Table 17. DC Load Diagnostics Control 2 Field Descriptions
      9. 10.6.9  DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
        1. Table 18. DC Load Diagnostics Control 3 Field Descriptions
      10. 10.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
        1. Table 19. DC Load Diagnostics Report 1 Field Descriptions
      11. 10.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
        1. Table 20. DC Load Diagnostics Report 2 Field Descriptions
      12. 10.6.12 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
        1. Table 21. DC Load Diagnostics Report 3 Line Output Field Descriptions
      13. 10.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
        1. Table 22. State-Reporting Field Descriptions
      14. 10.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
        1. Table 23. Channel Faults Field Descriptions
      15. 10.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
        1. Table 24. Global Faults 1 Field Descriptions
      16. 10.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
        1. Table 25. Global Faults 2 Field Descriptions
      17. 10.6.17 Warnings Register (address = 0x13) [default = 0x20]
        1. Table 26. Warnings Field Descriptions
      18. 10.6.18 Pin Control Register (address = 0x14) [default = 0x00]
        1. Table 27. Pin Control Field Descriptions
      19. 10.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
        1. Table 28. AC Load Diagnostic Control 1 Field Descriptions
      20. 10.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
        1. Table 29. AC Load Diagnostic Control 2 Field Descriptions
      21. 10.6.21 AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17–0x1A) [default = 0x00]
        1. Table 30. Chx AC LDG Impedance Report Field Descriptions
      22. 10.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
        1. Table 31. AC LDG Phase High Report Field Descriptions
      23. 10.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
        1. Table 32. AC LDG Phase Low Report Field Descriptions
      24. 10.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
        1. Table 33. AC LDG STI High Report Field Descriptions
      25. 10.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
        1. Table 34. Chx AC LDG STI Low Report Field Descriptions
      26. 10.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
        1. Table 35. Misc Control 3 Field Descriptions
      27. 10.6.27 Clip Control Register (address = 0x22) [default = 0x01]
        1. Table 36. Clip Control Field Descriptions
      28. 10.6.28 Clip Window Register (address = 0x23) [default = 0x14]
        1. Table 37. Clip Window Field Descriptions
      29. 10.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
        1. Table 38. Clip Warning Field Descriptions
      30. 10.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
        1. Table 39. ILIMIT Status Field Descriptions
      31. 10.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
        1. Table 40. Misc Control 4 Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 AM-Radio Band Avoidance
      2. 11.1.2 Parallel BTL Operation (PBTL)
      3. 11.1.3 Demodulation Filter Design
      4. 11.1.4 Line Driver Applications
    2. 11.2 Typical Applications
      1. 11.2.1 BTL Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Communication
        3. 11.2.1.3 Detailed Design Procedure
          1. 11.2.1.3.1 Hardware Design
          2. 11.2.1.3.2 Digital Input and the Serial Audio Port
          3. 11.2.1.3.3 Bootstrap Capacitors
          4. 11.2.1.3.4 Output Reconstruction Filter
        4. 11.2.1.4 Application Curves
      2. 11.2.2 PBTL Application
        1. 11.2.2.1 Design Requirements
          1. 11.2.2.1.1 Detailed Design Procedure
        2. 11.2.2.2 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Electrical Connection of Thermal pad and Heat Sink
      2. 13.1.2 EMI Considerations
      3. 13.1.3 General Guidelines
    2. 13.2 Layout Example
    3. 13.3 Thermal Considerations
  14. 14器件和文档支持
    1. 14.1 文档支持
      1. 14.1.1 相关文档
    2. 14.2 接收文档更新通知
    3. 14.3 社区资源
    4. 14.4 商标
    5. 14.5 静电放电警告
    6. 14.6 术语表
  15. 15机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

13.3 Thermal Considerations

The thermally enhanced PowerPAD package has an exposed pad up for connection to a heat sink. The output power of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on it by the system, such as the ambient operating temperature. The heat sink absorbs heat from the TAS6424M-Q1 and transfers it to the air. With proper thermal management this process can reach equilibrium and heat can be continually transferred from the device. Heat sinks can be smaller than that of classic linear amplifier design because of the excellent efficiency of class-D amplifiers. This device is intended for use with a heat sink, therefore, RθJC will be used as the thermal resistance from junction to the exposed metal package. This resistance will dominate the thermal management, so other thermal transfers will not be considered. The thermal resistance of RθJA (junction to ambient) is required to determine the full thermal solution. The thermal resistance is comprised of the following components:

  • RθJC of the TAS6424M-Q1
  • Thermal resistance of the thermal interface material
  • Thermal resistance of the heat sink

The thermal resistance of the thermal interface material can be determined from the manufacturer’s value for the area thermal resistance (expressed in °Cmm2/W) and the area of the exposed metal package. For example, a typical, white, thermal grease with a 0.0254 mm (0.001 inch) thick layer is approximately 4.52°C mm2/W. The TAS6424M-Q1 in the DKQ package has an exposed area of 47.6 mm2. By dividing the area thermal resistance by the exposed metal area determines the thermal resistance for the thermal grease. The thermal resistance of the thermal grease is 0.094°C/W

Table 41 lists the modeling parameters for one device on a heat sink. The junction temperature is assumed to be 115°C while delivering and average power of 10 watts per channel into a 4 Ω load. The thermal-grease example previously described is used for the thermal interface material. Use Equation 1 to design the thermal system.

Equation 1. RθJA = RθJC + thermal interface resistance + heat sink resistance

Table 41. Thermal Modeling

Description Value
Ambient Temperature 25°C
Average Power to load 40W (4 x 10W)
Power dissipation 8W (4 x 2W)
Junction Temperature 115°C
ΔT inside package 5.6°C (0.7°C/W × 8W)
ΔT through thermal interface material 0.75°C (0.094°C/W × 8W)
Required heat sink thermal resistance 10.45°C/W ([115°C – 25°C – 5.6°C – 0.75°C] / 8W)
System thermal resistance to ambient RθJA 11.24°C/W
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