ZHCSJB8 February   2019 TAS6424M-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     PCB 区域
  4. 4 修订历史记录
  5. 5 说明（续）
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Serial Audio Port
        1. 10.3.1.1 I2S Mode
        2. 10.3.1.2 Left-Justified Timing
        3. 10.3.1.3 Right-Justified Timing
        4. 10.3.1.4 TDM Mode
        5. 10.3.1.5 Supported Clock Rates
        6. 10.3.1.6 Audio-Clock Error Handling
      2. 10.3.2  High-Pass Filter
      3. 10.3.3  Volume Control and Gain
      4. 10.3.4  High-Frequency Pulse-Width Modulator (PWM)
      5. 10.3.5  Gate Drive
      6. 10.3.6  Power FETs
      7. 10.3.7  Load Diagnostics
        1. 10.3.7.1 DC Load Diagnostics
        2. 10.3.7.2 Line Output Diagnostics
        3. 10.3.7.3 AC Load Diagnostics
          1. 10.3.7.3.1 Impedance Magnitude Measurement
          2. 10.3.7.3.2 Impedance Phase Reference Measurement
          3. 10.3.7.3.3 Impedance Phase Measurement
      8. 10.3.8  Protection and Monitoring
        1. 10.3.8.1 Overcurrent Limit (ILIMIT)
        2. 10.3.8.2 Overcurrent Shutdown (ISD)
        3. 10.3.8.3 DC Detect
        4. 10.3.8.4 Clip Detect
        5. 10.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. 10.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. 10.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)
        8. 10.3.8.8 Overvoltage (OV) and Load Dump
      9. 10.3.9  Power Supply
        1. 10.3.9.1 Vehicle-Battery Power-Supply Sequence
        2. 10.3.9.2 Boosted Power-Supply Sequence
      10. 10.3.10 Hardware Control Pins
        1. 10.3.10.1 FAULT
        2. 10.3.10.2 WARN
        3. 10.3.10.3 MUTE
        4. 10.3.10.4 STANDBY
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operating Modes and Faults
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Communication Bus
      2. 10.5.2 I2C Bus Protocol
      3. 10.5.3 Random Write
      4. 10.5.4 Sequential Write
      5. 10.5.5 Random Read
      6. 10.5.6 Sequential Read
    6. 10.6 Register Maps
      1. 10.6.1  Mode Control Register (address = 0x00) [default = 0x00]
        1. Table 10. Mode Control Field Descriptions
      2. 10.6.2  Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
        1. Table 11. Misc Control 1 Field Descriptions
      3. 10.6.3  Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
        1. Table 12. Misc Control 2 Field Descriptions
      4. 10.6.4  SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
        1. Table 13. SAP Control Field Descriptions
      5. 10.6.5  Channel State Control Register (address = 0x04) [default = 0x55]
        1. Table 14. Channel State Control Field Descriptions
      6. 10.6.6  Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]
        1. Table 15. Ch x Volume Control Field Descriptions
      7. 10.6.7  DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
        1. Table 16. DC Load Diagnostics Control 1 Field Descriptions
      8. 10.6.8  DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
        1. Table 17. DC Load Diagnostics Control 2 Field Descriptions
      9. 10.6.9  DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
        1. Table 18. DC Load Diagnostics Control 3 Field Descriptions
      10. 10.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
        1. Table 19. DC Load Diagnostics Report 1 Field Descriptions
      11. 10.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
        1. Table 20. DC Load Diagnostics Report 2 Field Descriptions
      12. 10.6.12 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
        1. Table 21. DC Load Diagnostics Report 3 Line Output Field Descriptions
      13. 10.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
        1. Table 22. State-Reporting Field Descriptions
      14. 10.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
        1. Table 23. Channel Faults Field Descriptions
      15. 10.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
        1. Table 24. Global Faults 1 Field Descriptions
      16. 10.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
        1. Table 25. Global Faults 2 Field Descriptions
      17. 10.6.17 Warnings Register (address = 0x13) [default = 0x20]
        1. Table 26. Warnings Field Descriptions
      18. 10.6.18 Pin Control Register (address = 0x14) [default = 0x00]
        1. Table 27. Pin Control Field Descriptions
      19. 10.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
        1. Table 28. AC Load Diagnostic Control 1 Field Descriptions
      20. 10.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
        1. Table 29. AC Load Diagnostic Control 2 Field Descriptions
      21. 10.6.21 AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17–0x1A) [default = 0x00]
        1. Table 30. Chx AC LDG Impedance Report Field Descriptions
      22. 10.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
        1. Table 31. AC LDG Phase High Report Field Descriptions
      23. 10.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
        1. Table 32. AC LDG Phase Low Report Field Descriptions
      24. 10.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
        1. Table 33. AC LDG STI High Report Field Descriptions
      25. 10.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
        1. Table 34. Chx AC LDG STI Low Report Field Descriptions
      26. 10.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
        1. Table 35. Misc Control 3 Field Descriptions
      27. 10.6.27 Clip Control Register (address = 0x22) [default = 0x01]
        1. Table 36. Clip Control Field Descriptions
      28. 10.6.28 Clip Window Register (address = 0x23) [default = 0x14]
        1. Table 37. Clip Window Field Descriptions
      29. 10.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
        1. Table 38. Clip Warning Field Descriptions
      30. 10.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
        1. Table 39. ILIMIT Status Field Descriptions
      31. 10.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
        1. Table 40. Misc Control 4 Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 AM-Radio Band Avoidance
      2. 11.1.2 Parallel BTL Operation (PBTL)
      3. 11.1.3 Demodulation Filter Design
      4. 11.1.4 Line Driver Applications
    2. 11.2 Typical Applications
      1. 11.2.1 BTL Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Communication
        3. 11.2.1.3 Detailed Design Procedure
          1. 11.2.1.3.1 Hardware Design
          2. 11.2.1.3.2 Digital Input and the Serial Audio Port
          3. 11.2.1.3.3 Bootstrap Capacitors
          4. 11.2.1.3.4 Output Reconstruction Filter
        4. 11.2.1.4 Application Curves
      2. 11.2.2 PBTL Application
        1. 11.2.2.1 Design Requirements
          1. 11.2.2.1.1 Detailed Design Procedure
        2. 11.2.2.2 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Electrical Connection of Thermal pad and Heat Sink
      2. 13.1.2 EMI Considerations
      3. 13.1.3 General Guidelines
    2. 13.2 Layout Example
    3. 13.3 Thermal Considerations
  14. 14器件和文档支持
    1. 14.1 文档支持
      1. 14.1.1 相关文档
    2. 14.2 接收文档更新通知
    3. 14.3 社区资源
    4. 14.4 商标
    5. 14.5 静电放电警告
    6. 14.6 术语表
  15. 15机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.5 Electrical Characteristics

Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1 kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 79
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CURRENT
IPVDD_IDLE PVDD idle current All channels playing, no audio input 75 90 mA
IVBAT_IDLE VBAT idle current All channels playing, no audio input 90 100 mA
IPVDD_STBY PVDD standby current STANDBY Active, VDD = 0 V 0.5 1 μA
IVBAT_STBY VBAT standby current STANDBY Active, VDD = 0 V 4 6 μA
IVDD VDD supply current All channels playing, –60-dB signal 15 18 mA
OUTPUT POWER
PO_BTL Output power per channel, BTL 4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 20 22 W
4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 25 27
2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 38 40
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 42 45
4 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C 30 33
4 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C 40 45
PO_PBTL Output power per channel in parallel mode, PBTL 2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 35 40 W
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 45 50
1 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 72 80
1 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 80 90
2 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C 60 65
2 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C 75 80
EFFP Power efficiency 4 channels operating, 25 W output power/ch, 4 Ω load, PVDD = 14.4 V, TC = 25°C, including inductor losses(1) 86%
AUDIO PERFORMANCE
Vn Output noise voltage Zero input, A-weighting, gain level 1, PVDD = 14.4 V 42 μV
Zero input, A-weighting, gain level 2, PVDD = 14.4 V 55
Zero input, A-weighting, gain level 3, PVDD = 18 V 67
Zero input, A-weighting, gain level 4, PVDD = 18 V 85
GAIN Peak output voltage/dBFS Gain level 1, Register 0x01, bit 1-0 = 00 7.5 V/FS
Gain level 2, Register 0x01, bit 1-0 = 01 15
Gain level 3, Register 0x01, bit 1-0 = 10 21
Gain level 4, Register 0x01, bit 1-0 = 11 29
Crosstalk Channel crosstalk PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz –90 dB
PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz 75 dB
THD+N Total harmonic distortion + noise 0.02%
GCH Channel-to-channel gain variation –0.5 0 0.5 dB
LINE OUTPUT PERFORMANCE
Vn_LINEOUT Line output noise voltage Zero input, A-weighting, channel set to LINE MODE 42 μV
VO_LINEOUT Line output voltage 0-dB input, channel set to LINE MODE 5.5 VRMS
THD+N Line output total harmonic distortion + noise VO = 2 VRMS , channel set to LINE MODE 0.01%
DIGITAL INPUT PINS
VIH Input logic level high 70 %VDD
VIL Input logic level low 30 %VDD
IIH Input logic current, high VI = VDD 15 µA
IIL Input logic current, low VI = 0 –15 µA
PWM OUTPUT STAGE
RDS(on) FET drain-to-source resistance Not including bond wire and package resistance 90 mΩ
OVERVOLTAGE (OV) PROTECTION
VPVDD_OV PVDD overvoltage shutdown 19.3 20 22 V
VPVDD_OV_HYS PVDD overvoltage shutdown hysteresis 0.8 V
VVBAT_OV VBAT overvoltage shutdown 20 21.5 23 V
VVBAT_OV_HYS VBAT overvoltage shutdown hysteresis 0.6 V
UNDERVOLTAGE (UV) PROTECTION
VBATUV VBAT undervoltage shutdown 4 4.5 V
VBATUV_HYS VBAT undervoltage shutdown hysteresis 0.2 V
PVDDUV PVDD undervoltage shutdown 4 4.5 V
PVDDUV_HYS PVDD undervoltage shutdown hysteresis 0.2 V
BYPASS VOLTAGES
VGVDD Gate drive bypass pin voltage 7 V
VAVDD Analog bypass pin voltage 6 V
VVCOM Common bypass pin voltage 2.5 V
VVREG Regulator bypass pin voltage 5.5 V
POWER-ON RESET (POR)
VPOR VDD voltage for POR 2.1 2.7 V
VPOR_HY VDD POR recovery hysteresis voltage 0.5 V
OVERTEMPERATURE (OT) PROTECTION
OTW(i) Channel overtemperature warning 150 °C
OTSD(i) Channel overtemperature shutdown 175 °C
OTW Global junction overtemperature warning Set by register 0x01 bit 5-6, default value 130 °C
OTSD Global junction overtemperature shutdown 160 °C
OTHYS Overtemperature hysteresis 15 °C
LOAD OVER CURRENT PROTECTION
ILIM Overcurrent cycle-by-cycle limit OC Level 1 4 4.8 A
OC Level 2 6 6.5
ISD Overcurrent shutdown OC Level 1, Any short to supply, ground, or other channels 7 A
OC Level 2, Any short to supply, ground, or other channels 9
MUTE MODE
GMUTE Output attenuation 100 dB
CLICK AND POP
VCP Output click and pop voltage ITU-R 2k filter, High-Z/MUTE to Play, Play to Mute/High-Z 7 mV
DC OFSET
VOFFSET Output offset voltage 2 5 mV
DC DETECT
DCFAULT Output DC fault protection 2 2.5 V
DIGITAL OUTPUT PINS
VOH Output voltage for logic level high I = ±2 mA 90 %VDD
VOL Output voltage for logic level low I = ±2 mA 10 %VDD
tDELAY_CLIPDET Signal delay when output clipping detected 20 μs
LOAD DIAGNOSTICS
S2P Maximum resistance to detect a short from OUT pins to PVDD 500 Ω
S2G Maximum resistance to detect a short from OUT pins to ground 200 Ω
SL Shorted load detection tolerance Other channels in Hi-Z ±0.5 Ω
OL Open load Other channels in Hi-Z 40 70 Ω
TDC_DIAG DC diagnostic time All 4 Channels 230 ms
LO Line output 6 kΩ
TLINE_DIAG Line output diagnostic time 40 ms
ACIMP AC impedance accuracy Gain linearity, ƒ = 19 kHz, RL = 2 Ω to 16 Ω, 25%
Offset ±0.5 Ω
TAC_DIAG AC diagnostic time All 4 Channels 520 ms
I2C_ADDR PINS
tI2C_ADDR Time delay needed for I2C address set-up 300 μs
  1. Tested with Output Inductor DFEG7030D-3R3M.
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