8.4.4.2 Synchronous Type 1 Operating Mode

Synchronous type 1 operating mode is only supported on the user card interface. To enter synchronous operating mode, the user card interface goes through the synchronous type 1 activation sequence. Figure 4 shows the synchronous type 1 activation sequence.

CLKIN1 shall be low before the synchronous type 1 activation sequence is initiated. The following bit settings are required to initiate a synchronous type 1 activation sequence.

• ACTIVATION_TYPE (bit [6]; Reg 0x09) = 1
• CARD_TYPE (bit [7]; Reg 0x09) = 0
• START_SYNC (bit [0]; Reg 0x09) = 1

Figure 4. Synchronous Type 1 Activation Sequence

Once synchronous type 1 activation has been initiated, the following sequence of events occurs on the user card interface:

• VCCUC, RSTUC, CLKUC, C4, C8 and IOUC are all default low.
• V_CC is applied to the VCCUC pin per the SET_VCC_UC bit (bit[7:6]; Reg 0x01).
• After V_CC is stable RSTUC and CLKUC pulses are applied per t_S1-RST-HI and t_S1-CLK-HI defined in Table 2.
• After V_CC is stable, the IOUC line is pulled up to V_CC .
• After V_CC is stable C4 and C8 reflect the value in their corresponding I2C register bits (bit[5] and bit[4]; Reg 0x09).
• RSTUC is held low while the CLKUC line starts oscillating with a frequency of ~40Khz (generated from internal oscillator).
• The IO line is sampled on the 32 rising or falling (based on bit[1]; Reg 0x09) edges of CLK and stored in the FIFO registers 0AH to 0DH.
• At the end of the 32nd CLK pulse, the CLKUC is held low and the CLKUC pin is controlled by the clock settings register (Reg 0x02).
• IOUC is connected to IOMC1 if IO_EN_UC bit (bit[5] Reg 0x01) is set to 1.
• INT_SYNC_COMPLETE bit (Bit[1]; REG 0x41) is set and the INT line is asserted low.
• IOMC1 shall stay pulled up to V_DDI i.e. IOMC1 shall not be pulled low until INT is asserted.
• CLKIN1 shall toggle only after INT is asserted.
• RSTUC is controllable by I²C after INT is asserted.