8.4.4.3 Synchronous Type 2 Operating Mode

Synchronous type 2 operating mode is only supported on the user card interface. To enter synchronous operating mode, the user card interface goes through the synchronous type 2 activation sequence. Figure 5 shows the synchronous type 2 activation sequence.

CLKIN1 shall be low before the synchronous type 2 activation sequence is initiated. The following bit settings are required to initiate a synchronous type 1 activation sequence.

• ACTIVATION_TYPE (bit [6]; Reg 0x09) = 1
• CARD_TYPE (bit [7]; Reg 0x09) = 1
• START_SYNC (bit [0]; Reg 0x09) = 1

Figure 5. Synchronous Type 2 Activation Sequence

Once synchronous type 2 activation has been initiated, the following sequence of events occur on the user card interface:

• VCCUC, RSTUC, CLKUC, C4, C8 and IOUC are all default low.
• V_CC is applied to the VCCUC pin per the SET_VCC_UC bit (bit[7:6]; Reg 0x01).
• A single pulse is applied to CLKUC per the t_S2-CLK-HI timing defined in Table 3.
• The C4 line is held low through the V_CC ramp.
• The C4 line is released high per the t_S2-CLK-C4 timing defined in Table 3.
• After C4 is released CLKUC is controlled by clock settings register (Reg 0x02).
• After V_CC is stable, the IOUC line is pulled up to V_CC.
• After V_CC is stable, C8 reflects value in bit [4] Reg 0x09.
• IOUC is connected to IOMC1 if IO_EN_UC bit (bit[5] Reg 0x01) is set to 1.
• INT_SYNC_COMPLETE bit (Bit[1]; REG 0x41) is set and the INT line is asserted low.
• IOMC1 shall stay pulled up to V_DDI , that is, IOMC1 shall not be pulled low until INT is asserted.
• CLKIN1 shall toggle only after INT is asserted.
• RSTUC is controllable by I²C after INT is asserted.