8.4.4.6 Warm Reset Sequence

When a card interface is active in asynchronous mode, it is possible to initiate a warm reset sequence on the card interface. The warm reset sequence is initiated by setting the WARM bit (bit [3]) of the card interface settings register to ‘1’. Once warm reset is initiated the below sequence of events takes place on the card interface.

• V_CC is already ramped and stable per the SET_VCC bits (bit[7:6] of card interface settings register).
• CLK continues to oscillate per the card clock settings register.
• RST pin is pulled low (high before warm reset was initiated).
• C4 and C8 continue to reflect the value in their corresponding I²C register bits (bit[5] and bit[4]; Reg 0x09).
• IO stays connected to IOMC if IO_EN bit (bit5 of card interface settings register) is set to 1.
• Any change on the IO line during the first 200 card clock cycles after RST goes low is ignored.
• After the first 42100 CLK cycles, the RST line is driven high.
• If there is a high tow low transition on the IO line before RST is high, the EARLY bit (bit6) and MUTE bit (bit5) of the card interface status register (Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low.
• After RST is high, an internal counter starts counting CLK cycles. If there is a high to low transition on IO pin before the internal counter reaches the value defined by in the EARLY_COUNT_HI register (Reg 0x03 for user card, Reg 0x13 for SAM1, Reg 0x23 for SAM2, Reg 0x33 for SAM3) and EARLY_ COUNT_LO Register (Reg 0x04 for user card, Reg 0x14 for SAM1, Reg 0x24 for SAM2, Reg 0x34 for SAM3) then the EARLY bit in the card interface status register is set and INT is asserted.
• If the internal counter reaches the value defined by MUTE_COUNT_HI register (Reg 0x05 for user card, Reg 0x15 for SAM1, Reg 0x25 for SAM2, Reg 0x35 for SAM3) and MUTE_COUNT_LO (Reg 0x06 for user card, Reg 0x16 for SAM1, Reg 0x26 for SAM2, Reg 0x36 for SAM3) registers without a high to low transition on the IO line, then the MUTE bit in the card interface status registers is set and INT pin is asserted low.